JPH0595085A - Semiconductor diffused layer resistance - Google Patents

Abstract

PURPOSE:To provide a semiconductor diffused layer resistance which is able to inclease a degree of freedom for the circuit design by making thinner an interlayer insulating film so that a threshold voltage of a parasitic MOS transistor including the interlayer insulating film as a gate insulating film, flow of a leak current between resistances can be prevented and a metal wiring can be laid freely on a diffused resistance forming region via the interlayer insulating film. CONSTITUTION:A diffused layer resistance forming region 103 is provided with shallow channel stopper layer 110 of which conductivity-type is opposite to that of a resistance diffused layer 106 which has lower impurity concentration and shallower impurity depth than those of the resistance diffused layer 106. Therefore, metal wirings can be laid freely on the diffused layer resistance forming region 103 via the interlayer insulating film and a degree of freedom for circuit design can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor diffusion layer resistance, and more particularly to a semiconductor diffusion layer resistance which prevents leakage current due to surface inversion between diffusion layers.

[0002]

2. Description of the Related Art A semiconductor diffusion layer resistor used in a bipolar integrated circuit or the like is superior to a polycrystalline semiconductor layer resistor in absolute accuracy and relative accuracy, and is particularly indispensable for a linear circuit. FIG. 3A is a top view of the diffusion layer resistance used in the conventional bipolar integrated circuit.
A cross-sectional view taken along the line AA ₁ in (a) is shown in FIG. Three
01 is a P ⁻ type semiconductor substrate, 302 is an N ⁺ type buried layer for preventing latch-up by a parasitic thyristor,
Reference numeral 303 is an N ⁻ type epitaxial region, 304 is a P ⁺ type insulating isolation diffusion region, and 305 is an insulating isolation oxide film. The P-type diffusion layer resistor 306 is formed by diffusing a P-type impurity into the P ⁺ -type insulation isolation diffusion region 304 and the N ⁻ -type epitaxial region 303 surrounded by the insulation isolation oxide film 305. As a method of introducing the P-type impurity, the ion implantation method is generally used at present, and is significantly superior to the thermal diffusion method and the like in terms of accuracy and miniaturization. 307 is B
Interlayer insulating film such as PSG (boron phosphorus silicate glass), 30
Reference numeral 8 is a contact hole, and 309 is a metal wiring such as aluminum.

[0003]

SUMMARY OF THE INVENTION In recent integrated circuits,
With the progress of miniaturization, the interlayer insulating film has been thinned accordingly. On the other hand, the power supply voltage remains the same, and the mainstream is 5V, and there are still bipolar integrated circuits of 12V type, 40V type, and medium / high withstand voltage type. Therefore, in the conventional diffusion layer resistance structure, for example, as shown in FIG.
When the power supply voltage is applied to the terminal B shown in (a) and the terminal C is connected to the ground, the surface of the N ⁻ type epitaxial layer in the resistance forming region causes P type inversion because the interlayer insulating film 307 is thin, There has been a problem that a leak current flows between the resistors.

In the prior art, in order to solve this problem, an insulating isolation oxide film is provided between the resistors to prevent surface inversion as shown in FIG. 4, but with this method, the element is miniaturized. Will be hindered.

An object of the present invention is to provide a semiconductor diffusion layer resistor for a semiconductor integrated circuit, which can suppress a decrease in threshold voltage of a parasitic MOS transistor when an interlayer insulating film is thinned and prevent a leak current. To do.

[0006]

A semiconductor diffusion layer resistance of the present invention comprises a first conductivity type insulation isolation region or a second conductivity type resistance formation region surrounded by an insulation isolation oxide film, and a first conductivity type impurity. And a second conductivity type channel stopper layer having a shallower impurity depth and a lower impurity concentration than the diffusion layer resistance region.

[0007]

The present invention will be described below with reference to the drawings. FIG. 1A is a structural cross-sectional view of a semiconductor diffusion layer resistor according to an embodiment of the present invention. 101 is a P ⁻ type semiconductor substrate, 10
2 is an N ⁺ type buried layer for preventing latch-up, 103 is an N ⁻ type epitaxial region, 104 is a P ⁺ type insulating isolation region, 1
Reference numeral 05 denotes an insulating isolation oxide film, and 106 denotes a P-type diffusion resistance region, which is the same as the conventional diffusion layer resistance shown in FIG.

A feature of the present invention is to have an N ⁻ type channel stopper region 110. The impurity depth of this channel stopper region is shallower than that of the resistance region 106, and the impurity concentration is low. 107 is an interlayer insulating film, 108
Is a contact hole, and 109 is a metal wiring layer. Figure 1
(B) shows the depth profile of a-a ₁ cross section and b-b ₁ cross section in FIG. 1 (a). As can be seen from this profile, since the N-type channel stopper region was formed in the portion that was a conventional epitaxial region (b-b ₁ cross section), the impurity concentration on the surface was high, and surface inversion did not occur easily. For example, the epitaxial layer concentration of the conventional example is 5 × 10 ¹⁵ cm ⁻³ , and the surface concentration of the N-type channel stopper region of the present invention is 1 × 10 ¹⁷ cm 3.
Assuming ^-3 , the theoretical threshold value of the difference between the threshold voltages of the parasitic MOS transistors having the interlayer insulating films 107 and 307 as their gate insulating films is about 35 V, which is higher in the present invention.

On the other hand, as can be seen from the profile of the aa ₁ cross section, the junction at the bottom of the P-type resistor has a P-type resistor whose impurity depth is deeper than the depth of the N-type channel stopper. It is a junction between the resistance layer and the N ⁻ type epitaxial layer, and although the junction capacitance increases a little on the side surface of the resistance region, it can take the same value as the conventional value on the bottom surface. Moreover, the depth of the resistance layer is generally 0.2 to
Although the width of the resistance layer is as short as 0.5 μm, which is a value several orders of magnitude higher than the width of the resistance layer, the area ratio of the side surface portion to the bottom surface portion of the resistance region per unit length is 1:10 to 1:30. The increase in parasitic capacitance on the side surface can be almost ignored. In high-speed devices of recent years, RC due to increase in parasitic capacitance
Although the increase of the time constant becomes a problem, in the present invention, the parasitic capacitance can be suppressed to almost the same as that of the conventional technique.

FIG. 2 is a sectional view showing a second embodiment of the present invention. In the first embodiment, the N-type channel stopper layer is formed by introducing impurities into the entire surface of the diffusion resistance forming region, whereas in the present embodiment, the N-type channel stopper layer is formed by selectively introducing impurities between the resistors. The N-type channel stopper layer 210 is formed, and the N-type channel stopper layer 210 and the P-type diffusion layer 204 are formed.
Does not make a direct bond. For this reason,
The junction capacitance has the same value as that of the conventional technique, and the junction breakdown voltage is improved as compared with the first embodiment. Although the area of the resistance forming region is slightly increased as compared with the first embodiment, it can be suppressed to be smaller than that of the conventional technique using the insulating isolation oxide film.

[0011]

As described above, according to the present invention, in the second conductivity type region forming the first conductivity type diffusion layer resistance, the impurity concentration is lower and the impurity depth is lower than that of the first conductivity type resistance diffusion layer. By providing the second-conductivity-type channel stopper layer having a shallow thickness, it is possible to suppress a decrease in the threshold voltage of the parasitic MOS transistor when the interlayer insulating film is thinned and to prevent a leak current. .. Therefore, the metal wiring can be freely passed through the diffusion resistance forming region via the interlayer insulating film, and the degree of freedom in circuit design is improved.

Further, since the bottom surface of the resistance diffusion layer does not form a junction with the channel stopper layer, the junction capacitance can be suppressed to the same level as in the conventional case, and the speedup of the integrated circuit is not hindered.

[Brief description of drawings]

Impurity profile of the resistive diffusion layer and the channel stopper layer in FIG. 1 of the semiconductor chip of an embodiment of the present invention cross-sectional view and its a-a ₁ and b-b _1.

FIG. 2 is a sectional view of a semiconductor chip according to another embodiment of the present invention.

FIG. 3 is a schematic top view and a sectional view taken along line AA _{1 of a} conventional semiconductor diffusion layer resistance forming region.

FIG. 4 is a sectional view of a semiconductor chip showing a conventional technique for preventing a leak current between resistors.

[Explanation of symbols]

101, 201, 301, 401 P ⁻ type semiconductor substrate 102, 202, 302, 402 N ⁺ type buried layer 103, 203, 303, 403 N ⁻ type epitaxial region 104, 204, 304, 404 P ⁺ type insulating isolation diffusion region 105, 205, 305, 405 Insulation isolation oxide film 106, 206, 306, 406 P-type diffusion resistance region 107, 207, 307, 407 Inter-layer insulation film 108, 208, 308, 408 Contact hole 109, 209, 309, 409 Metal Wiring 110, 210 N-type channel stopper layer

Claims (3)

[Claims] 1. A semiconductor diffusion layer resistor formed by diffusing a first conductivity type impurity into a desired shape in a first conductivity type insulation isolation region or a second conductivity type semiconductor region surrounded by an insulation isolation oxide film. 2. The semiconductor diffusion layer resistance according to the item 2, wherein the second conductivity type resistance forming region has a channel stopper layer into which a second conductivity type impurity having a higher concentration than that of the resistance forming region is introduced. 2. The semiconductor diffusion layer resistance according to claim 1, wherein the channel stopper layer has a lower impurity concentration and a shallower impurity depth than those of the diffusion layer resistance region of the first conductivity type. .. 3. The channel stopper layer is selectively provided between resistors so as not to form a junction with the resistance diffusion layer of the first conductivity type.
The semiconductor diffusion layer resistance described.