JPS6435744U - - Google Patents
Info
- Publication number
- JPS6435744U JPS6435744U JP13119587U JP13119587U JPS6435744U JP S6435744 U JPS6435744 U JP S6435744U JP 13119587 U JP13119587 U JP 13119587U JP 13119587 U JP13119587 U JP 13119587U JP S6435744 U JPS6435744 U JP S6435744U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- semiconductor device
- base part
- wire
- view
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 3
- 230000001681 protective effect Effects 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
第１図は、この考案の半導体装置を製作するた
めのリードフレームを示す平面図、第２図は、第
１図のＡ―Ａ線に沿う断面図、第３図は、上記半
導体装置の使用例を示す斜視図、第４図は、従来
のこの種の半導体装置を製作するためのリードフ
レームを示す平面図、第５図は、上記従来の半導
体装置の断面図、第６図は、上記従来の半導体装
置の使用例を示す一部切欠斜視図である。 １１ａ，１１ｂ……連結部、１２ａ……リード
部、１２ｂ……支持部、１２ｃ……幅広先端部、
１３……ベース部、１４……リードフレーム、１
５……半導体チツプ、１６……金属細線、１７…
…間隙、１８……絶縁部材、１９……表面保護部
材、２０……導体パターン、２１……回路基板、
２２……半田、２３……半導体装置。
めのリードフレームを示す平面図、第２図は、第
１図のＡ―Ａ線に沿う断面図、第３図は、上記半
導体装置の使用例を示す斜視図、第４図は、従来
のこの種の半導体装置を製作するためのリードフ
レームを示す平面図、第５図は、上記従来の半導
体装置の断面図、第６図は、上記従来の半導体装
置の使用例を示す一部切欠斜視図である。 １１ａ，１１ｂ……連結部、１２ａ……リード
部、１２ｂ……支持部、１２ｃ……幅広先端部、
１３……ベース部、１４……リードフレーム、１
５……半導体チツプ、１６……金属細線、１７…
…間隙、１８……絶縁部材、１９……表面保護部
材、２０……導体パターン、２１……回路基板、
２２……半田、２３……半導体装置。
Claims (1)
- 半導体チツプが載置されるベース部と、このベ
ース部に載置された前記半導体チツプの電極金属
と金属細線によりワイヤボンデイングされるリー
ド部とを有し、前記ベース部およびリード部の裏
面側の一部に、絶縁部材が貼付され、前記半導体
チツプを含む主面側のみに保護部材を備えたこと
を特徴とする半導体装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987131195U JPH0543477Y2 (ja) | 1987-08-28 | 1987-08-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987131195U JPH0543477Y2 (ja) | 1987-08-28 | 1987-08-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6435744U true JPS6435744U (ja) | 1989-03-03 |
| JPH0543477Y2 JPH0543477Y2 (ja) | 1993-11-02 |
Family
ID=31387034
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987131195U Expired - Lifetime JPH0543477Y2 (ja) | 1987-08-28 | 1987-08-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0543477Y2 (ja) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5396969U (ja) * | 1978-01-10 | 1978-08-07 |
-
1987
- 1987-08-28 JP JP1987131195U patent/JPH0543477Y2/ja not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5396969U (ja) * | 1978-01-10 | 1978-08-07 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0543477Y2 (ja) | 1993-11-02 |