JPS6435442U - - Google Patents
Info
- Publication number
- JPS6435442U JPS6435442U JP12831587U JP12831587U JPS6435442U JP S6435442 U JPS6435442 U JP S6435442U JP 12831587 U JP12831587 U JP 12831587U JP 12831587 U JP12831587 U JP 12831587U JP S6435442 U JPS6435442 U JP S6435442U
- Authority
- JP
- Japan
- Prior art keywords
- host computer
- direct memory
- data
- counter
- counts
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012986 modification Methods 0.000 claims 1
- 230000004048 modification Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は本考案を実施したＩ／Ｏチヤネル制御
装置の構成を表わす図、第２図は従来のＩ／Ｏチ
ヤネル制御装置の構成を表わす図である。
１０……Ｉ／Ｏチヤネル制御装置、１１……ダ
イレクト・メモリ・アクセス制御部、１２……バ
ツフア・メモリ、１３……Ｉ／Ｏチヤネル・イン
ターフエイス、１４……ダイレクト・メモリ・ア
クセス転送カウンタ、１５……チヤネル・データ
・カウンタ、１６……カウンタ制御部、２……ホ
スト計算機、２１……ホスト・メモリ、３……デ
バイス、ＳＢ……システム・バス。
FIG. 1 is a diagram showing the configuration of an I/O channel control device embodying the present invention, and FIG. 2 is a diagram showing the configuration of a conventional I/O channel control device. 10... I/O channel control device, 11... Direct memory access control unit, 12... Buffer memory, 13... I/O channel interface, 14... Direct memory access transfer counter, 15... Channel data counter, 16... Counter control unit, 2... Host computer, 21... Host memory, 3... Device, SB... System bus.
Claims (1)
ホスト計算機側と前記デバイスとの間でデータを
転送するダイレクト・メモリ・アクセス制御部と
、このダイレクト・メモリ・アクセス回数をカウ
ントするダイレクト・メモリ・アクセス転送カウ
ンタとを有するＩ／Ｏチヤネル制御装置において
、前記デバイスとの間でデータ転送数をカウント
し、前記ホスト計算機から読み出し可能であると
ともに前記デバイスからカウント値修正要求を受
信する受信手段を有するチヤネル・データ・カウ
ンタを設けることを特徴とするＩ／Ｏチヤネル制
御装置。 a direct memory access control unit that is installed between a host computer and a device and that transfers data between the host computer and the device; and a direct memory access transfer that counts the number of direct memory accesses. an I/O channel control device having a counter that counts the number of data transfers to and from the device, is readable from the host computer, and has a receiving unit that receives a count value modification request from the device; An I/O channel control device comprising a data counter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12831587U JPS6435442U (en) | 1987-08-24 | 1987-08-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12831587U JPS6435442U (en) | 1987-08-24 | 1987-08-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6435442U true JPS6435442U (en) | 1989-03-03 |
Family
ID=31381539
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12831587U Pending JPS6435442U (en) | 1987-08-24 | 1987-08-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6435442U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4991342A (en) * | 1972-12-29 | 1974-08-31 |
-
1987
- 1987-08-24 JP JP12831587U patent/JPS6435442U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4991342A (en) * | 1972-12-29 | 1974-08-31 |
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