JPS6435390A - Fast circuit test system - Google Patents

Fast circuit test system

Info

Publication number
JPS6435390A
JPS6435390A JP62192166A JP19216687A JPS6435390A JP S6435390 A JPS6435390 A JP S6435390A JP 62192166 A JP62192166 A JP 62192166A JP 19216687 A JP19216687 A JP 19216687A JP S6435390 A JPS6435390 A JP S6435390A
Authority
JP
Japan
Prior art keywords
sampling
clock
output
test system
generator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62192166A
Other languages
Japanese (ja)
Inventor
Taketoshi Ikegami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Yokogawa Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Electric Corp filed Critical Yokogawa Electric Corp
Priority to JP62192166A priority Critical patent/JPS6435390A/en
Publication of JPS6435390A publication Critical patent/JPS6435390A/en
Pending legal-status Critical Current

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  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE:To determine the phase relation of sampling and to obtain a high- performance, fast test system by generating the trigger of a test signal and a sampling clock by utilizing a clock inputted to a pattern generator. CONSTITUTION:First and second sampling parts 30 and 31 consisting of samplers 5 and data acquisition circuits 6 are provided. The output f2 of a clock generator 32 is connected as a timing signal to the 1st sampling part 30 and the output f1 of a clock generator 32 is frequency-divided by a frequency divider 9 and connected to the 2nd sampling part 31. Further, the output f1 of the clock generator 32 is connected to a pattern generator. Then the frequency division ratio of the frequency divider 9 is equalized to the number of bits of a test signal and the ratio of clocks of the outputs f1 and f2 is obtained by adding the extent of a shift in phase to the number of bits, thus determining the phase relation between the 1st and 2nd sampling parts.
JP62192166A 1987-07-31 1987-07-31 Fast circuit test system Pending JPS6435390A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62192166A JPS6435390A (en) 1987-07-31 1987-07-31 Fast circuit test system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62192166A JPS6435390A (en) 1987-07-31 1987-07-31 Fast circuit test system

Publications (1)

Publication Number Publication Date
JPS6435390A true JPS6435390A (en) 1989-02-06

Family

ID=16286785

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62192166A Pending JPS6435390A (en) 1987-07-31 1987-07-31 Fast circuit test system

Country Status (1)

Country Link
JP (1) JPS6435390A (en)

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