JPS6430364A - Area designation circuit - Google Patents

Area designation circuit

Info

Publication number
JPS6430364A
JPS6430364A JP62184672A JP18467287A JPS6430364A JP S6430364 A JPS6430364 A JP S6430364A JP 62184672 A JP62184672 A JP 62184672A JP 18467287 A JP18467287 A JP 18467287A JP S6430364 A JPS6430364 A JP S6430364A
Authority
JP
Japan
Prior art keywords
time
control
address
memory
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62184672A
Other languages
Japanese (ja)
Inventor
Hiroshi Arai
Kazuo Murai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP62184672A priority Critical patent/JPS6430364A/en
Publication of JPS6430364A publication Critical patent/JPS6430364A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To simplify the hardwares by controlling a sequence control at the time of write but the control of only video line clock at the time of read and separating an address into a division for main scanning direction switching and a subscanning direction switching. CONSTITUTION:At the time of writing in a memory 11 to store the main- scanning-direction address of an area-switching point as data, both the data and the address are controlled in accordance with a sequence, hence an interruption can be executed independently of the clock for video and line, but at the time of reading, the control is achieved only with a video line clock. Also, the address is divided into two divisions; one is for a main-scanning direction switching and the other for subscanning direction switching, and at the time of writing, subscanning direction information is added in order that a function to process both read data and video data in real time. In such a way, the read and write from and in the memory 111 can be completely separated into the sequence-control and the hardware control by a clock, therefore, one memory can be used in common for a write and a read. As a result, the constitution of the hardwares in the vicinity of the memory can be simplified.
JP62184672A 1987-07-25 1987-07-25 Area designation circuit Pending JPS6430364A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62184672A JPS6430364A (en) 1987-07-25 1987-07-25 Area designation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62184672A JPS6430364A (en) 1987-07-25 1987-07-25 Area designation circuit

Publications (1)

Publication Number Publication Date
JPS6430364A true JPS6430364A (en) 1989-02-01

Family

ID=16157339

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62184672A Pending JPS6430364A (en) 1987-07-25 1987-07-25 Area designation circuit

Country Status (1)

Country Link
JP (1) JPS6430364A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5778289A (en) * 1980-10-31 1982-05-15 Toshiba Corp Picture information mask circuit
JPS60121878A (en) * 1983-12-06 1985-06-29 Dainippon Screen Mfg Co Ltd Duplicating system of picture scanning

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5778289A (en) * 1980-10-31 1982-05-15 Toshiba Corp Picture information mask circuit
JPS60121878A (en) * 1983-12-06 1985-06-29 Dainippon Screen Mfg Co Ltd Duplicating system of picture scanning

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