JPS6430328A - D/a converter - Google Patents

D/a converter

Info

Publication number
JPS6430328A
JPS6430328A JP18728687A JP18728687A JPS6430328A JP S6430328 A JPS6430328 A JP S6430328A JP 18728687 A JP18728687 A JP 18728687A JP 18728687 A JP18728687 A JP 18728687A JP S6430328 A JPS6430328 A JP S6430328A
Authority
JP
Japan
Prior art keywords
data
frequency
sampling clock
converter
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18728687A
Other languages
Japanese (ja)
Inventor
Fukunori Sekiguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP18728687A priority Critical patent/JPS6430328A/en
Publication of JPS6430328A publication Critical patent/JPS6430328A/en
Pending legal-status Critical Current

Links

Landscapes

  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To make the frequency of a necessary sampling clock into fs with respective D/A converters by providing N pieces of D/A converters in parallel to input data in which the data are inserted and a repetitive frequency is made into Nfs. CONSTITUTION:The digital data of a sample frequency fs through an input terminal 10 are made into the data DA of a sampling frequency 2fs with a digital filter 11, a switching circuit 12 is switched by a switching control signal SW from a timing signal forming circuit 15, odd numbered data DA0 are supplied to a D/A converter 13, even numbered data DAE are supplied to a D/A converter 14, and converted to the analog data by sampling clock pulses SP0 and SPE from the circuit 15. The folding of a frequency fs/2 or above removed, synthesized alternately from a switching circuit 17 and not needed by a low pass filter 18 is removed. Thus, the sampling clock frequency of respective D/A converting parts may be the fs.
JP18728687A 1987-07-27 1987-07-27 D/a converter Pending JPS6430328A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18728687A JPS6430328A (en) 1987-07-27 1987-07-27 D/a converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18728687A JPS6430328A (en) 1987-07-27 1987-07-27 D/a converter

Publications (1)

Publication Number Publication Date
JPS6430328A true JPS6430328A (en) 1989-02-01

Family

ID=16203341

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18728687A Pending JPS6430328A (en) 1987-07-27 1987-07-27 D/a converter

Country Status (1)

Country Link
JP (1) JPS6430328A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5210739A (en) * 1988-11-14 1993-05-11 Asahi Kogaku Kogyo Kabushiki Kaisha Carriage lock apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5210739A (en) * 1988-11-14 1993-05-11 Asahi Kogaku Kogyo Kabushiki Kaisha Carriage lock apparatus

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