JPS642977B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device, and more particularly to a debug information storage method for storing debug information.

Conventionally, debugging functions include a function to store the instruction transition and a function to store the hardware status, either of which can be used separately or by initializing with a switch, etc.; the former requires a large amount of hardware; The latter had the drawback of not being able to obtain all the necessary information.

The purpose of the present invention is to classify the information necessary for debugging into macro information and micro information, and store the older information in the same memory as macro information and the newer information in the same memory. The objective is to obtain the information necessary for debugging without increasing the amount of time required.

That is, in the present invention, the information necessary for debugging exists in the form of macro information (for example, OP code) and micro information (micro instructions), and micro information must be stored within the scope of one macro information. By taking advantage of this advantageous feature and providing individual registers for addresses to store each piece of information, debugging information can be obtained in chronological order.

The present invention will be explained in detail below with reference to the drawings.

FIG. 1 shows an embodiment of the invention.

In the figure, IR is a register that stores macro debug information, MR is a register that stores micro debug information, MEM is a memory for storing information,
IBAR is a register circuit that sets a memory address for storing information when storing macro debug information, MBAR is a register circuit that sets a memory address for storing information when storing micro debug information, MUX is a multiplexer circuit, CONT
is the control circuit, and RR is the output circuit.

In Figure 1, the contents of register IR, which stores macro instructions (OP codes) to be stored in information storage memory MEM, and the contents of register MR, which stores micro instructions being executed, are stored in a multiplex circuit. Input via MUX.

The address of the information storage memory MEM is specified by register IBAR when storing macro instructions, and by register when storing micro instructions.
Conducted by MR.

The information stored in the information storage memory MEM is output to the output circuit.
Output to RR.

When the control circuit CONT receives the end signal of one macro instruction, it stores the contents of the register IR in the information storage memory MEM using the contents of the register IBAR as an address, and also increments the register IBAR by one.

At that time, the value obtained by adding 1 to register IBAR is set in register MBAR.

Register MBAR when microinstruction is started
The contents of the register MR are stored in the information storage memory MEM using the contents of the register MR as the address of the information storage memory MEM.

At that time, the contents of register MBAR are updated by +1.

From the control circuit CONT, flag information is input to the information storage memory MEM to distinguish whether the information to be stored is the contents of the register IR or the contents of the register MR. For example, if it is the contents of the register IR, it is set to "1"
If it is the contents of register MR, input "0".

Next, when the control circuit CONT receives the end signal of the next macro instruction, it uses the contents of the register IBAR as an address and stores the register IR in the information storage memory MEM.
Stores the contents of and increments IBAR by 1.

In this case, the next microinstruction will be stored at the storage address location of the previously stored microinstruction, but as mentioned earlier, the microinstruction (microinstruction) is replaced by one corresponding macroinstruction (macroinstruction ) as long as it is stored within the range of
I don't mind anything.

FIG. 2 is a diagram showing the storage state of macro instructions and micro instructions in the information storage memory MEM.

According to this embodiment, macro instructions and micro instructions can be written in chronological order by simply adding a simple control circuit, an address register (IBAR or MBAR), and a multiplexer circuit (MUX) without having duplicate memory for information storage. It has the effect of being able to be stored.

In the example shown in Figure 1, macro instructions and micro instructions are stored, but in addition to macro instructions and micro instructions, each address may be stored, or both each instruction and address may be stored. You may also do so.

Furthermore, based on the same inventive idea, by changing the information stored in IR and MR regarding the combination of macro and micro operations (for example, IR
(Set flag information for memory access such as operand read, write, and instruction read in MR, set detailed information in MR, and input memory access end signal instead of instruction end signal to control circuit). Can provide sufficient functionality.

According to the present invention, macro information and micro information can be stored in chronological order, and it is possible to provide necessary and sufficient functions for debugging at low cost.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the invention. FIG. 2 is a diagram showing the storage state of macro instructions and micro instructions in the information storage memory MEM. In the figure, IR is a register that stores macro debug information, MR is a register that stores micro debug information, MEM is a memory for storing information,
IBAR is a register circuit that sets a memory address for storing information when storing macro debug information, MBAR is a register circuit that sets a memory address for storing information when storing micro debug information, MUX is a multiplexer circuit, CONT
is the control circuit, and RR is the output circuit.

Claims (1)

[Claims] 1. In a debug information storage method for a data processing device in which each sequentially executed macro operation is composed of a series of micro operations, there is provided a memory for storing debug information and a memory for storing macro debug information. A first register for setting an address for storing micro debug information, a second register for setting an address for storing micro debug information, and a first register for selecting either macro debug information or micro debug information. a multiplexer for selecting one of the first and second registers, and a second multiplexer for selecting one of the first and second registers, and each time a macro operation is completed, the macro debug information selected by the first multiplexer is storing the address of the contents of a first register selected by the second multiplexer of the memory, incrementing the contents of the first register, and transferring the incremented value to the second register; and at the end of each micro operation, the micro debug information selected by the first multiplexer is transferred to the contents of the second register selected by the second multiplexer of the memory. 1. A debug information storage method characterized in that the debug information is stored at the address of the second register and the contents of the second register are incremented.