JPS6429036A - Pcm communication equipment with cyclic code inspection - Google Patents

Pcm communication equipment with cyclic code inspection

Info

Publication number
JPS6429036A
JPS6429036A JP18456487A JP18456487A JPS6429036A JP S6429036 A JPS6429036 A JP S6429036A JP 18456487 A JP18456487 A JP 18456487A JP 18456487 A JP18456487 A JP 18456487A JP S6429036 A JPS6429036 A JP S6429036A
Authority
JP
Japan
Prior art keywords
circuit
cyclic code
counter
code inspection
frame synchronization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18456487A
Other languages
Japanese (ja)
Inventor
Seiichi Suga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP18456487A priority Critical patent/JPS6429036A/en
Publication of JPS6429036A publication Critical patent/JPS6429036A/en
Pending legal-status Critical Current

Links

Landscapes

  • Detection And Prevention Of Errors In Transmission (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To improve the quality of a PCM circuit by feeding back the result of cyclic code inspection to a clock input gate circuit through a counter and a shift circuit. CONSTITUTION:A PCM signal from a PCM signal input terminal 1 is inputted to a frame synchronization detection circuit 2. When the frame synchronization detection circuit 2 detects frame synchronization, it opens the gate of the clock input gate circuit 4, and sends a clock to a frame synchronization counter 5. A cyclic code inspection circuit 7 compares a check bit for the cyclic code inspection in the PCM signal and the cyclic code inspection value of the PCM signal, and when the comparison results in discordance, it counts up an error counter 8. When the count-up of the error counter 8 reaches a prescribed value, a counter circuit 9 closes the clock input gate circuit 4 for one clock portion, and delays the frame synchronization counter 5 and a timing generation circuit 6, and delays a frame synchronizing timing signal.
JP18456487A 1987-07-23 1987-07-23 Pcm communication equipment with cyclic code inspection Pending JPS6429036A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18456487A JPS6429036A (en) 1987-07-23 1987-07-23 Pcm communication equipment with cyclic code inspection

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18456487A JPS6429036A (en) 1987-07-23 1987-07-23 Pcm communication equipment with cyclic code inspection

Publications (1)

Publication Number Publication Date
JPS6429036A true JPS6429036A (en) 1989-01-31

Family

ID=16155413

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18456487A Pending JPS6429036A (en) 1987-07-23 1987-07-23 Pcm communication equipment with cyclic code inspection

Country Status (1)

Country Link
JP (1) JPS6429036A (en)

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