JPS57186859A - Frame synchronizing circuit - Google Patents

Frame synchronizing circuit

Info

Publication number
JPS57186859A
JPS57186859A JP56070661A JP7066181A JPS57186859A JP S57186859 A JPS57186859 A JP S57186859A JP 56070661 A JP56070661 A JP 56070661A JP 7066181 A JP7066181 A JP 7066181A JP S57186859 A JPS57186859 A JP S57186859A
Authority
JP
Japan
Prior art keywords
counter
pulse
frame
detecting
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56070661A
Other languages
Japanese (ja)
Inventor
Masaharu Hata
Kota Kinoshita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP56070661A priority Critical patent/JPS57186859A/en
Publication of JPS57186859A publication Critical patent/JPS57186859A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0602—Systems characterised by the synchronising information used

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To quickly secure frame synchronization even in case of a circuit of an inferior quality, by resetting a frame counter in the event of continuous dissidence of a frane pattern detecting output of an output of the frame counter. CONSTITUTION:When a detecting pulse is generated from a frame pattern detecting circuit 1 for the first time, an FF 9 of a waiting circuit 7 is set, and also a detecting pulse input gate of the FF 9 is stopped. This detecting pulse sets an FF 8, too, and releases a clock input of a frame counter 6. A frame pulse outputted from a terminal Cp of the counter 6 resets the counter 6 itself, and also its time position with the detecting pulse from the circuit 1 is compared by a gate 13. Subsequently, when a dissidence pulse of both the pulses has been generated by the number N set by a counter 12, the counter 12 generates a pulse. This pulse resets the counter 6 forcibly, and also stops an input of the counter 6. Also, it resets the FF 9, and releases the detecting pulse input gate of the FF 9.
JP56070661A 1981-05-13 1981-05-13 Frame synchronizing circuit Pending JPS57186859A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56070661A JPS57186859A (en) 1981-05-13 1981-05-13 Frame synchronizing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56070661A JPS57186859A (en) 1981-05-13 1981-05-13 Frame synchronizing circuit

Publications (1)

Publication Number Publication Date
JPS57186859A true JPS57186859A (en) 1982-11-17

Family

ID=13438060

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56070661A Pending JPS57186859A (en) 1981-05-13 1981-05-13 Frame synchronizing circuit

Country Status (1)

Country Link
JP (1) JPS57186859A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6042957A (en) * 1983-08-19 1985-03-07 Sanyo Electric Co Ltd Detecting circuit of frame synchronizing signal
JPS61199952U (en) * 1985-06-01 1986-12-15

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49107129A (en) * 1973-02-12 1974-10-11
JPS5552652A (en) * 1978-10-13 1980-04-17 Nippon Telegr & Teleph Corp <Ntt> Frame synchronizing unit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49107129A (en) * 1973-02-12 1974-10-11
JPS5552652A (en) * 1978-10-13 1980-04-17 Nippon Telegr & Teleph Corp <Ntt> Frame synchronizing unit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6042957A (en) * 1983-08-19 1985-03-07 Sanyo Electric Co Ltd Detecting circuit of frame synchronizing signal
JPS61199952U (en) * 1985-06-01 1986-12-15

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