JPS6426232A - Microprogram control system for pipeline computer - Google Patents

Microprogram control system for pipeline computer

Info

Publication number
JPS6426232A
JPS6426232A JP18264487A JP18264487A JPS6426232A JP S6426232 A JPS6426232 A JP S6426232A JP 18264487 A JP18264487 A JP 18264487A JP 18264487 A JP18264487 A JP 18264487A JP S6426232 A JPS6426232 A JP S6426232A
Authority
JP
Japan
Prior art keywords
microcode
stage
branch
branch destination
execution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18264487A
Other languages
Japanese (ja)
Inventor
Tsuyoshi Mori
Masayuki Okada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18264487A priority Critical patent/JPS6426232A/en
Publication of JPS6426232A publication Critical patent/JPS6426232A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To speed up microprogram branching in an arithmetic stage while suppressing an increase in hardware quantity by setting a branch destination microcode read out of a control storage in a 1st stage in a microcode register corresponding to a specific stage. CONSTITUTION:When a conditional branch microcode and the branch destination microcode based upon the decision result of a branch condition are executed at the time of the execution of a machine instruction, the conditional branch microcode is read out to a microcode register (A)7 for controlling a stage A and executed in the order of stages A7 M8 E9 W10. The branch destination microcode to be necessary according to the decision result of the branch condition of the branch destination microcode in the stage E9 is read so that the execution of the branch destination microcode in the stage E9 is performed following the execution of the branch microcode in the stage E9. Consequently, the microprogram branching in the arithmetic stage is speeded up while suppressing an increase in the hardware quantity.
JP18264487A 1987-07-22 1987-07-22 Microprogram control system for pipeline computer Pending JPS6426232A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18264487A JPS6426232A (en) 1987-07-22 1987-07-22 Microprogram control system for pipeline computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18264487A JPS6426232A (en) 1987-07-22 1987-07-22 Microprogram control system for pipeline computer

Publications (1)

Publication Number Publication Date
JPS6426232A true JPS6426232A (en) 1989-01-27

Family

ID=16121907

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18264487A Pending JPS6426232A (en) 1987-07-22 1987-07-22 Microprogram control system for pipeline computer

Country Status (1)

Country Link
JP (1) JPS6426232A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04364527A (en) * 1991-06-11 1992-12-16 Gijutsu Kenkyu Kumiai Kokusai Fuajii Kogaku Kenkyusho Arithmetic unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04364527A (en) * 1991-06-11 1992-12-16 Gijutsu Kenkyu Kumiai Kokusai Fuajii Kogaku Kenkyusho Arithmetic unit

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