JPS57161943A - Data processing device - Google Patents

Data processing device

Info

Publication number
JPS57161943A
JPS57161943A JP4647881A JP4647881A JPS57161943A JP S57161943 A JPS57161943 A JP S57161943A JP 4647881 A JP4647881 A JP 4647881A JP 4647881 A JP4647881 A JP 4647881A JP S57161943 A JPS57161943 A JP S57161943A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
instruction
means
operands
decoding means
operand
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4647881A
Other versions
JPS6160459B2 (en )
Inventor
Tadaaki Bando
Hideo Maejima
Hidekazu Matsumoto
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802Instruction prefetching

Abstract

PURPOSE:To obtain a data processing device where variable length instructions are executed in a high speed, by providing specific instruction buffer means, instruction aligner, operation code decoding means, and operand designator decoding means. CONSTITUTION:An instruction buffer means which reads an instruction from a memory 301, where instructiions and operands are stored, and holds it and an instruction aligner means 305 which takes out an instruction including an operand designator from the instruction buffer means are provided. An operation code decoding means which specifies the operand designator included in the taken-out instruction and specifies the function of the instruction and an operand designator decoding means 309 adre provided. The instruction aligner means and the operation code decoding means prepare different operands so that operand designators of one or more operands are decoded in one machine cycle, and thus, the pipe-line processing among plural operands is performed.
JP4647881A 1981-03-31 1981-03-31 Expired JPS6160459B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4647881A JPS6160459B2 (en) 1981-03-31 1981-03-31

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4647881A JPS6160459B2 (en) 1981-03-31 1981-03-31

Publications (2)

Publication Number Publication Date
JPS57161943A true true JPS57161943A (en) 1982-10-05
JPS6160459B2 JPS6160459B2 (en) 1986-12-20

Family

ID=12748298

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4647881A Expired JPS6160459B2 (en) 1981-03-31 1981-03-31

Country Status (1)

Country Link
JP (1) JPS6160459B2 (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62226231A (en) * 1986-03-27 1987-10-05 Toshiba Corp Processor
JPS63113634A (en) * 1986-10-30 1988-05-18 Nec Corp Relative address calculation system for program counter
JPH0221332A (en) * 1988-07-11 1990-01-24 Fujitsu Ltd Microprocessor
JPH02110639A (en) * 1988-10-20 1990-04-23 Fujitsu Ltd Filing system
WO1990008355A1 (en) * 1989-01-17 1990-07-26 Fujitsu Limited Microprocessor
JPH04123865U (en) * 1991-04-23 1992-11-10
USRE40498E1 (en) 1993-05-27 2008-09-09 Matsushita Electric Industrial Co., Ltd. Variable address length compiler and processor improved in address management
JP5609875B2 (en) * 2009-07-31 2014-10-22 旭硝子株式会社 Sealing glass for semiconductor devices, sealing materials, sealing materials paste, and a semiconductor device and a manufacturing method thereof

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62226231A (en) * 1986-03-27 1987-10-05 Toshiba Corp Processor
JPH0523447B2 (en) * 1986-03-27 1993-04-02 Tokyo Shibaura Electric Co
JPS63113634A (en) * 1986-10-30 1988-05-18 Nec Corp Relative address calculation system for program counter
JPH0221332A (en) * 1988-07-11 1990-01-24 Fujitsu Ltd Microprocessor
JPH02110639A (en) * 1988-10-20 1990-04-23 Fujitsu Ltd Filing system
WO1990008355A1 (en) * 1989-01-17 1990-07-26 Fujitsu Limited Microprocessor
US5249273A (en) * 1989-01-17 1993-09-28 Fujitsu Limited Microprocessor having a variable length instruction format
JPH04123865U (en) * 1991-04-23 1992-11-10
USRE40498E1 (en) 1993-05-27 2008-09-09 Matsushita Electric Industrial Co., Ltd. Variable address length compiler and processor improved in address management
USRE41959E1 (en) 1993-05-27 2010-11-23 Panasonic Corporation Variable address length compiler and processor improved in address management
JP5609875B2 (en) * 2009-07-31 2014-10-22 旭硝子株式会社 Sealing glass for semiconductor devices, sealing materials, sealing materials paste, and a semiconductor device and a manufacturing method thereof

Also Published As

Publication number Publication date Type
JPS6160459B2 (en) 1986-12-20 grant

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