JPS6424622A - Level detection circuit - Google Patents

Level detection circuit

Info

Publication number
JPS6424622A
JPS6424622A JP18204387A JP18204387A JPS6424622A JP S6424622 A JPS6424622 A JP S6424622A JP 18204387 A JP18204387 A JP 18204387A JP 18204387 A JP18204387 A JP 18204387A JP S6424622 A JPS6424622 A JP S6424622A
Authority
JP
Japan
Prior art keywords
signal
level detection
circuit
level
detection signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18204387A
Other languages
Japanese (ja)
Inventor
Hiroshi Nakajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP18204387A priority Critical patent/JPS6424622A/en
Publication of JPS6424622A publication Critical patent/JPS6424622A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To facilitate the level detection by providing an OR circuit ORing a level detection signal obtained from a peak detector circuit and a level detection signal being a high frequency signal separated from the 2nd flip-flop circuit in a measuring electronic circuit network or the like. CONSTITUTION:Since a signal width of a low level is large and the signal width of a high level is increased gradually in a level detection signal masked at first, a terminal voltage across a capacitor 15, that is, a signal (k) has a signal form curved downward. Since the signal width is changed reversely in case of the signal masked at first in the level detection signal masked at the 2nd, the signal waveform is curved upward. The signal (k) is supplied a peak detector 17 and a peak detector circuit 17 detects the peak level of the signal (k) to extract the level detection signal (j). Then the signals (j) and (l) are inputted to an OR circuit 18, which outputs a level detection signal (m).
JP18204387A 1987-07-21 1987-07-21 Level detection circuit Pending JPS6424622A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18204387A JPS6424622A (en) 1987-07-21 1987-07-21 Level detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18204387A JPS6424622A (en) 1987-07-21 1987-07-21 Level detection circuit

Publications (1)

Publication Number Publication Date
JPS6424622A true JPS6424622A (en) 1989-01-26

Family

ID=16111343

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18204387A Pending JPS6424622A (en) 1987-07-21 1987-07-21 Level detection circuit

Country Status (1)

Country Link
JP (1) JPS6424622A (en)

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