JPS6423552A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enlarge utility efficiency of a transistor region on a chip and to improve the degree of integration of the chip, by disposing a row of cells longitudinarily on a base so that intervals between a row of cells are not made constant in a longitudinal channel and they are varied according to crowdedness of wirings in a similar channel. CONSTITUTION:A row of cells are first composed in four rows, and channel intervals between them are estimated to determine their folding positions (shown in dotted lines). Next the cells are folded and the channel intervals between a row of cells are estimated again. A row of cells on the central part and on the end parts are moved individually to be disposed on a base. Lengths of the folded parts in each row of cells can be set according to crowdedness of the wiring and length of the cells. Only end parts on one side can be folded like a row of cells 4c and 4d. The channel intervals can be set freely in the unit of transistor rows. Namely, after the initial estimation of the channel intervals, the folding positions of a row of cells are determined according to the crowdedness of the wirings, and second estimation of the channel intervals is performed while the cells are folded, so that the disposal position is determined. Hence, ineffective regions on the chip can be reduced without being accompanied by complexity in the disposal method, and also the degree of integration can be improved.