JPS6421581U

JPS6421581U -

Info

Publication number: JPS6421581U
Application number: JP11602187U
Authority: JP
Priority date: 1987-07-28
Filing date: 1987-07-28
Publication date: 1989-02-02

Description

[Brief explanation of the drawing]

第１図はこの考案の一実施例を示すＡＧＣ回路
図、第２図は基準電圧の波形図で、ａはＰＡＬＢ
／Ｇ方式の場合、ｂはＳＥＣＡＭＬ方式の場合、
第３図は従来のＡＧＣ回路図、第４図はＡＧＣル
ープのブロツク結線図を示す。図において、１は入力端子、２，３はＮＰＮト
ランジスタ、４は定電流源、５，６はペデスタル
バイアス電圧、７はスイツチ、８，９は負荷抵抗
、１２，１３はＮＰＮトランジスタ、１４は定電
流源、１５は抵抗、１６はＰＮＰトランジスタ、
１７はダイオード、１８は出力端子、２６，２７
はＮＰＮトランジスタ、２８，２９は抵抗である
。なお、図中、同一符号は同一、または相当部分
を示す。 Figure 1 is an AGC circuit diagram showing an embodiment of this invention, Figure 2 is a reference voltage waveform diagram, and a is a PALB circuit diagram.
/G method, b is SECAML method,
FIG. 3 shows a conventional AGC circuit diagram, and FIG. 4 shows a block connection diagram of an AGC loop. In the figure, 1 is an input terminal, 2 and 3 are NPN transistors, 4 is a constant current source, 5 and 6 are pedestal bias voltages, 7 is a switch, 8 and 9 are load resistances, 12 and 13 are NPN transistors, and 14 is a constant current source. Current source, 15 is a resistor, 16 is a PNP transistor,
17 is a diode, 18 is an output terminal, 26, 27
is an NPN transistor, and 28 and 29 are resistors. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims

[Scope of utility model registration request]

A video intermediate device characterized by having a detector that switches both the reference level and conversion gain between positive video modulation and negative video modulation, and sets at least the conversion gain higher during negative modulation than during positive modulation. Automatic gain control device for frequency processing circuits.