JPH0377562U - - Google Patents
Info
- Publication number
- JPH0377562U JPH0377562U JP13817189U JP13817189U JPH0377562U JP H0377562 U JPH0377562 U JP H0377562U JP 13817189 U JP13817189 U JP 13817189U JP 13817189 U JP13817189 U JP 13817189U JP H0377562 U JPH0377562 U JP H0377562U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- voltage
- pedestal
- variable gain
- sync chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 5
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Television Receiver Circuits (AREA)
Description
第１図はこの考案の１つの実施例に係る映像信
号のオートゲインコントロール回路を示すブロツ
ク図、第２図は第１図の動作を示すタイムチヤー
トである。
主な符号の説明、１０……電圧制御可変利得増
幅器、１２……シンクチツプ−ペデスタル間電圧
検出回路、２６……演算増幅回路。
FIG. 1 is a block diagram showing an automatic gain control circuit for a video signal according to one embodiment of this invention, and FIG. 2 is a time chart showing the operation of FIG. 1. Explanation of main symbols: 10... Voltage controlled variable gain amplifier, 12... Sink chip-pedestal voltage detection circuit, 26... Operational amplifier circuit.
Claims (1)
チツプ−ペデスタル間の電圧を検出するシンクチ
ツプ−ペデスタル間電圧検出回路と、 シンクチツプ−ペデスタル間電圧検出回路の検
出電圧と所定の参照電圧の差電圧を求める演算回
路と、 を有し、演算回路の出力電圧に基づき可変利得回
路に負帰還を掛けたこと、 を特徴とする映像信号のオートゲインコントロー
ル回路。[Claims for Utility Model Registration] A variable gain circuit that inputs a video signal, a sync chip-pedestal voltage detection circuit that detects the voltage between the sync chip and the pedestal of the video signal output from the variable gain circuit, and a sync chip-pedestal voltage detection circuit. An arithmetic circuit for calculating a voltage difference between a detection voltage of a voltage detection circuit and a predetermined reference voltage; and a variable gain circuit subjected to negative feedback based on the output voltage of the arithmetic circuit. gain control circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13817189U JPH0377562U (en) | 1989-11-29 | 1989-11-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13817189U JPH0377562U (en) | 1989-11-29 | 1989-11-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0377562U true JPH0377562U (en) | 1991-08-05 |
Family
ID=31685292
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13817189U Pending JPH0377562U (en) | 1989-11-29 | 1989-11-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0377562U (en) |
-
1989
- 1989-11-29 JP JP13817189U patent/JPH0377562U/ja active Pending
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