JPS6421561A - Processor controller - Google Patents

Processor controller

Info

Publication number
JPS6421561A
JPS6421561A JP17598387A JP17598387A JPS6421561A JP S6421561 A JPS6421561 A JP S6421561A JP 17598387 A JP17598387 A JP 17598387A JP 17598387 A JP17598387 A JP 17598387A JP S6421561 A JPS6421561 A JP S6421561A
Authority
JP
Japan
Prior art keywords
processor
signal
interruption
controller
hold request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17598387A
Other languages
Japanese (ja)
Inventor
Toshimichi Seki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP17598387A priority Critical patent/JPS6421561A/en
Publication of JPS6421561A publication Critical patent/JPS6421561A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24Handling requests for interconnection or transfer for access to input/output bus using interrupt

Abstract

PURPOSE:To execute other processing without stopping a processor even a hold request signal by converting the hold request signal into an interruption signal by an interruption controller and applying the converted signal to the processor. CONSTITUTION:The system is constituted so that a hold request signal from a main controller 4 is inputted to the interruption controller 17 and converted into an interruption signal and the interruption signal is applied to the processor 1. Namely, a common bus 2 is connected to the processor 1, the controller 17, the main controller 4 and I/O means 3a, 3b are connected to the common bus 2, another bus 5 is connected to the processor 1, and another I/O means 6 is connected to the bus 5. Since the controller 17 converts the hold request signal from the main controller 4 into the interruption signal and applies the interruption signal to the processor 1, another I/O means 6 can be accessed without stopping the processor 1.
JP17598387A 1987-07-16 1987-07-16 Processor controller Pending JPS6421561A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17598387A JPS6421561A (en) 1987-07-16 1987-07-16 Processor controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17598387A JPS6421561A (en) 1987-07-16 1987-07-16 Processor controller

Publications (1)

Publication Number Publication Date
JPS6421561A true JPS6421561A (en) 1989-01-24

Family

ID=16005647

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17598387A Pending JPS6421561A (en) 1987-07-16 1987-07-16 Processor controller

Country Status (1)

Country Link
JP (1) JPS6421561A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05324348A (en) * 1992-05-20 1993-12-07 Nec Corp Single chip microcomputer
JP2007272554A (en) * 2006-03-31 2007-10-18 Renesas Technology Corp Data processor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05324348A (en) * 1992-05-20 1993-12-07 Nec Corp Single chip microcomputer
JP2007272554A (en) * 2006-03-31 2007-10-18 Renesas Technology Corp Data processor

Similar Documents

Publication Publication Date Title
CA2011503A1 (en) Multiprocessor system
AU585076B2 (en) Interrupt handling in a multiprocessor computing system
JPS5427741A (en) Information processing organization
EP0231595A3 (en) Input/output controller for a data processing system
MY102292A (en) Mode conversion of computer commands
JPS6421561A (en) Processor controller
JPS53102643A (en) Interrupt processing system for computer
JPS5255350A (en) System recomposition control unit
JPS5295939A (en) Common contrl device for input/output
JPS6476306A (en) Reset controller
JPS5336149A (en) Information processing system
JPS6431252A (en) Data bus width transformer
JPS56159726A (en) Bus request processor
JPS57206974A (en) Shared memory control circuit
JPS6436245A (en) Signal processor
JPS5325784A (en) Analog input signal takein system
JPS55123704A (en) Maintenance device of control unit
JPS5567822A (en) Channel connection system
JPS57136240A (en) Peripheral device switching device
JPS5735433A (en) Connector
JPS6476257A (en) Common bus control system
CA2006382A1 (en) Method of controlling arithmetic pipeline configuration in multiprocessor system
JPS5760435A (en) Data transfer controlling system
JPS5421229A (en) Data fetch system
JPS6473447A (en) System for controlling low order device