JPS6421561A - Processor controller - Google Patents
Processor controllerInfo
- Publication number
- JPS6421561A JPS6421561A JP17598387A JP17598387A JPS6421561A JP S6421561 A JPS6421561 A JP S6421561A JP 17598387 A JP17598387 A JP 17598387A JP 17598387 A JP17598387 A JP 17598387A JP S6421561 A JPS6421561 A JP S6421561A
- Authority
- JP
- Japan
- Prior art keywords
- processor
- signal
- interruption
- controller
- hold request
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
Abstract
PURPOSE:To execute other processing without stopping a processor even a hold request signal by converting the hold request signal into an interruption signal by an interruption controller and applying the converted signal to the processor. CONSTITUTION:The system is constituted so that a hold request signal from a main controller 4 is inputted to the interruption controller 17 and converted into an interruption signal and the interruption signal is applied to the processor 1. Namely, a common bus 2 is connected to the processor 1, the controller 17, the main controller 4 and I/O means 3a, 3b are connected to the common bus 2, another bus 5 is connected to the processor 1, and another I/O means 6 is connected to the bus 5. Since the controller 17 converts the hold request signal from the main controller 4 into the interruption signal and applies the interruption signal to the processor 1, another I/O means 6 can be accessed without stopping the processor 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17598387A JPS6421561A (en) | 1987-07-16 | 1987-07-16 | Processor controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17598387A JPS6421561A (en) | 1987-07-16 | 1987-07-16 | Processor controller |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6421561A true JPS6421561A (en) | 1989-01-24 |
Family
ID=16005647
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17598387A Pending JPS6421561A (en) | 1987-07-16 | 1987-07-16 | Processor controller |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6421561A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05324348A (en) * | 1992-05-20 | 1993-12-07 | Nec Corp | Single chip microcomputer |
JP2007272554A (en) * | 2006-03-31 | 2007-10-18 | Renesas Technology Corp | Data processor |
-
1987
- 1987-07-16 JP JP17598387A patent/JPS6421561A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05324348A (en) * | 1992-05-20 | 1993-12-07 | Nec Corp | Single chip microcomputer |
JP2007272554A (en) * | 2006-03-31 | 2007-10-18 | Renesas Technology Corp | Data processor |
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