JPS6476257A - Common bus control system - Google Patents

Common bus control system

Info

Publication number
JPS6476257A
JPS6476257A JP23223887A JP23223887A JPS6476257A JP S6476257 A JPS6476257 A JP S6476257A JP 23223887 A JP23223887 A JP 23223887A JP 23223887 A JP23223887 A JP 23223887A JP S6476257 A JPS6476257 A JP S6476257A
Authority
JP
Japan
Prior art keywords
common bus
gate
control
processors
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23223887A
Other languages
Japanese (ja)
Inventor
Takatoshi Suzuki
Yoshihiro Sato
Takeshi Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Telecom Technologies Ltd
Original Assignee
Hitachi Telecom Technologies Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Telecom Technologies Ltd filed Critical Hitachi Telecom Technologies Ltd
Priority to JP23223887A priority Critical patent/JPS6476257A/en
Publication of JPS6476257A publication Critical patent/JPS6476257A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To realize a common bus using system with a low cost circuit constitution by connecting plural processors to a common bus by a bidirectional or a single direction gate in parallel and providing a control part for opening and closing the gate at a certain cycle. CONSTITUTION:The bidirectional gate 8 is used between the common bus 13 and the processors 1-4 to connect them. A bus controller 7 is operated at a timing synchronizing with the processor to control the four processors by the combination of signals INT1, INT0 and apply a common bus use permitting signal. At the same timing, a common bus control signal (GATE signal) is transmitted to attain a control by opening and closing the bidirectional gate. IN such a way, the common bus using system is realized with the compact circuit constitution and the low cost by a few bus signal lines and control elements to many processors.
JP23223887A 1987-09-18 1987-09-18 Common bus control system Pending JPS6476257A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23223887A JPS6476257A (en) 1987-09-18 1987-09-18 Common bus control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23223887A JPS6476257A (en) 1987-09-18 1987-09-18 Common bus control system

Publications (1)

Publication Number Publication Date
JPS6476257A true JPS6476257A (en) 1989-03-22

Family

ID=16936138

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23223887A Pending JPS6476257A (en) 1987-09-18 1987-09-18 Common bus control system

Country Status (1)

Country Link
JP (1) JPS6476257A (en)

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