JPS6417123A - Vector random number generating device - Google Patents

Vector random number generating device

Info

Publication number
JPS6417123A
JPS6417123A JP62174365A JP17436587A JPS6417123A JP S6417123 A JPS6417123 A JP S6417123A JP 62174365 A JP62174365 A JP 62174365A JP 17436587 A JP17436587 A JP 17436587A JP S6417123 A JPS6417123 A JP S6417123A
Authority
JP
Japan
Prior art keywords
bits
random number
vector
number generating
generating device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62174365A
Other languages
Japanese (ja)
Inventor
Makoto Tajo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62174365A priority Critical patent/JPS6417123A/en
Publication of JPS6417123A publication Critical patent/JPS6417123A/en
Pending legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE:To produce an inspection vector pseudo random number having reproducibility one by one at high speed by using a vector random number generating instruction for the production of the pseudo random numbers using an (m) series and executing said generating instruction with a hardware. CONSTITUTION:The (p) bits serving as the initial value are stored in a temporary holding means 2 through a signal line 1. Then the (m) bits obtained by shifting the (m) bits to the left by (p-q) bits are applied to an EX-OR 3 together with lower level (m) bits of first (p) bits. Thus an exclusive OR is secured at every bit. The output (m) bits of the EX-OR 3 is connected to the high-order level (p-m) bits out of the (p) bits of the means 2. Thus the (p) bits are obtained as the new initializing value and supplied to the means 2. Then the 2-bit binary random numbers are outputted out of the output (m) bits of the EX-OR 3 at every clock.
JP62174365A 1987-07-13 1987-07-13 Vector random number generating device Pending JPS6417123A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62174365A JPS6417123A (en) 1987-07-13 1987-07-13 Vector random number generating device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62174365A JPS6417123A (en) 1987-07-13 1987-07-13 Vector random number generating device

Publications (1)

Publication Number Publication Date
JPS6417123A true JPS6417123A (en) 1989-01-20

Family

ID=15977344

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62174365A Pending JPS6417123A (en) 1987-07-13 1987-07-13 Vector random number generating device

Country Status (1)

Country Link
JP (1) JPS6417123A (en)

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