JPS6413736U - - Google Patents
Info
- Publication number
- JPS6413736U JPS6413736U JP1987110258U JP11025887U JPS6413736U JP S6413736 U JPS6413736 U JP S6413736U JP 1987110258 U JP1987110258 U JP 1987110258U JP 11025887 U JP11025887 U JP 11025887U JP S6413736 U JPS6413736 U JP S6413736U
- Authority
- JP
- Japan
- Prior art keywords
- solid
- image sensor
- sealing member
- frame body
- state image
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003384 imaging method Methods 0.000 claims description 4
- 238000007789 sealing Methods 0.000 claims description 4
- 239000012790 adhesive layer Substances 0.000 claims description 2
- 239000000919 ceramic Substances 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Transforming Light Signals Into Electric Signals (AREA)
- Solid State Image Pick-Up Elements (AREA)
Description
第1図は本考案の固体撮像素子収納用パツケー
ジの一実施例を示す断面図、第2図は第1図に示
す固体撮像素子収納用パツケージに使用される封
止部材の一部破断斜視図、第3図は従来の固体撮
像素子収納用パツケージの断面図、第4図は第3
図に示す固体撮像素子収納用パツケージの蓋体の
底面図である。 1:基体、2:蓋体、8:封止部材、8a:枠
体、8b:接着材層。
ジの一実施例を示す断面図、第2図は第1図に示
す固体撮像素子収納用パツケージに使用される封
止部材の一部破断斜視図、第3図は従来の固体撮
像素子収納用パツケージの断面図、第4図は第3
図に示す固体撮像素子収納用パツケージの蓋体の
底面図である。 1:基体、2:蓋体、8:封止部材、8a:枠
体、8b:接着材層。
Claims (1)
- 内部に固体撮像素子を収容するための空所を有
するセラミツクス製基体と少なくとも一部が透光
性である蓋体とから成り、基体上に蓋体を封止部
材を介し取着することによつて内部空所を気密に
封止するようになした固体撮像素子収納パツケー
ジにおいて、前記封止部材が熱膨張係数40乃至
100×10−7/℃の枠体と該枠体の外表面に
取着された接着材層から成ることを特徴とする固
体撮像素子収納用パツケージ。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987110258U JPS6413736U (ja) | 1987-07-17 | 1987-07-17 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987110258U JPS6413736U (ja) | 1987-07-17 | 1987-07-17 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6413736U true JPS6413736U (ja) | 1989-01-24 |
Family
ID=31347253
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1987110258U Pending JPS6413736U (ja) | 1987-07-17 | 1987-07-17 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6413736U (ja) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59132146A (ja) * | 1983-01-18 | 1984-07-30 | Toshiba Corp | 半導体装置のパツケ−ジング方法 |
-
1987
- 1987-07-17 JP JP1987110258U patent/JPS6413736U/ja active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59132146A (ja) * | 1983-01-18 | 1984-07-30 | Toshiba Corp | 半導体装置のパツケ−ジング方法 |