JPS635652U - - Google Patents
Info
- Publication number
- JPS635652U JPS635652U JP9875786U JP9875786U JPS635652U JP S635652 U JPS635652 U JP S635652U JP 9875786 U JP9875786 U JP 9875786U JP 9875786 U JP9875786 U JP 9875786U JP S635652 U JPS635652 U JP S635652U
- Authority
- JP
- Japan
- Prior art keywords
- solid
- insulating base
- image sensor
- state image
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 claims description 2
- 238000003384 imaging method Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Solid State Image Pick-Up Elements (AREA)
Description
第１図は本考案の固体撮像素子収納用パツケー
ジの一実施例を示す断面図、第２図は第１図の固
体撮像素子収納用パツケージの絶縁基体の平面図
、第３図は従来の固体撮像素子収納用パツケージ
の断面図、第４図は第３図の固体撮像素子収納用
パツケージの絶縁基体の平面図である。 １：絶縁基体、２：蓋体、７：金属板、８：貫
通孔。
ジの一実施例を示す断面図、第２図は第１図の固
体撮像素子収納用パツケージの絶縁基体の平面図
、第３図は従来の固体撮像素子収納用パツケージ
の断面図、第４図は第３図の固体撮像素子収納用
パツケージの絶縁基体の平面図である。 １：絶縁基体、２：蓋体、７：金属板、８：貫
通孔。
Claims (1)
- 絶縁基体と少なくとも一部が透光性である蓋体
とから成り、内部に固体撮像素子を収納するため
の空所を有する固体撮像素子収納用パツケージに
おいて、前記絶縁基体の底面に、該絶縁基体の位
置合わせを行うための治具が挿入される貫通孔を
有する金属板を取着したことを特徴とする固体撮
像素子収納用パツケージ。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9875786U JPS635652U (ja) | 1986-06-26 | 1986-06-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9875786U JPS635652U (ja) | 1986-06-26 | 1986-06-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS635652U true JPS635652U (ja) | 1988-01-14 |
Family
ID=30967011
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9875786U Pending JPS635652U (ja) | 1986-06-26 | 1986-06-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS635652U (ja) |
-
1986
- 1986-06-26 JP JP9875786U patent/JPS635652U/ja active Pending