JPS6413611A - Microcomputer - Google Patents

Microcomputer

Info

Publication number
JPS6413611A
JPS6413611A JP62169020A JP16902087A JPS6413611A JP S6413611 A JPS6413611 A JP S6413611A JP 62169020 A JP62169020 A JP 62169020A JP 16902087 A JP16902087 A JP 16902087A JP S6413611 A JPS6413611 A JP S6413611A
Authority
JP
Japan
Prior art keywords
microcomputer
oscillation
signal line
clock stop
power backup
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62169020A
Other languages
Japanese (ja)
Inventor
Kazuhiko Ikemoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62169020A priority Critical patent/JPS6413611A/en
Publication of JPS6413611A publication Critical patent/JPS6413611A/en
Pending legal-status Critical Current

Links

Classifications

    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Power Sources (AREA)
  • Microcomputers (AREA)

Abstract

PURPOSE:To prevent a supply current from flowing out through an external feedback resistance, by setting the output of an oscillating tristate inverter of an oscillator to the high impedance state by an oscillation clock stop signal when a microcomputer is set to the oscillation clock stop state for power backup. CONSTITUTION:When the microcomputer is set to the oscillation clock stop state for power backup, an oscillation clock stop signal line 10 goes to the high level and a control signal line 12 goes to the low level, and the output of a tristate inverter 2 for oscillation is set to the high impedance state independently of the input. Since a clock input control transistor 9 of the microcomputer is turned on, a clock input signal line 11 of the microcomputer is fixed to the low level. The current consumption for power backup of the microcomputer is reduced because a route where the current flows out through an external feedback resistance 5 does not exists in the oscillator.
JP62169020A 1987-07-07 1987-07-07 Microcomputer Pending JPS6413611A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62169020A JPS6413611A (en) 1987-07-07 1987-07-07 Microcomputer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62169020A JPS6413611A (en) 1987-07-07 1987-07-07 Microcomputer

Publications (1)

Publication Number Publication Date
JPS6413611A true JPS6413611A (en) 1989-01-18

Family

ID=15878840

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62169020A Pending JPS6413611A (en) 1987-07-07 1987-07-07 Microcomputer

Country Status (1)

Country Link
JP (1) JPS6413611A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090049324A1 (en) * 2007-08-13 2009-02-19 Rambus, Inc. Methods and systems for operating memory in two modes

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090049324A1 (en) * 2007-08-13 2009-02-19 Rambus, Inc. Methods and systems for operating memory in two modes
US8332680B2 (en) * 2007-08-13 2012-12-11 Rambus Inc. Methods and systems for operating memory in two modes

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