JPS6412564A - Pin grid array type package - Google Patents

Pin grid array type package

Info

Publication number
JPS6412564A
JPS6412564A JP16924687A JP16924687A JPS6412564A JP S6412564 A JPS6412564 A JP S6412564A JP 16924687 A JP16924687 A JP 16924687A JP 16924687 A JP16924687 A JP 16924687A JP S6412564 A JPS6412564 A JP S6412564A
Authority
JP
Japan
Prior art keywords
connecting pin
package
conductors
substrate
grid array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16924687A
Other languages
Japanese (ja)
Inventor
Akira Aso
Kazumi Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP16924687A priority Critical patent/JPS6412564A/en
Publication of JPS6412564A publication Critical patent/JPS6412564A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To make a plurality of signals and the power be transmitted through one connecting pin so as to enable a package to be miniaturized and multifunctional concurrently by a method wherein one connecting pin is connected with an outer circuit through a plurality of conductors which are insulated along in an axial direction. CONSTITUTION:A pin-shaped insulator axis section 21 and two conductors 22a and 22b which are circumferentially connected with the axis section 21 in an axial direction are provided on a package substrate 1 and a plurality of connecting pins 2 used for connection with an external circuit are disposed in matrix in such a manner as they penetrate the substrate 1 and protrude out of it. And, one ends are connected with the inner face of the substrate 1 through the conductors 22a and 22b of each connecting pin 2 and lands 31 and the other ends are connected with corresponding electrodes of a semiconductor chip through a plurality of wirings 3. Then, plural signals and the power are transmitted through the one connecting pin 2, so that a package can be easily made to be miniaturized and multi-functional.
JP16924687A 1987-07-06 1987-07-06 Pin grid array type package Pending JPS6412564A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16924687A JPS6412564A (en) 1987-07-06 1987-07-06 Pin grid array type package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16924687A JPS6412564A (en) 1987-07-06 1987-07-06 Pin grid array type package

Publications (1)

Publication Number Publication Date
JPS6412564A true JPS6412564A (en) 1989-01-17

Family

ID=15882951

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16924687A Pending JPS6412564A (en) 1987-07-06 1987-07-06 Pin grid array type package

Country Status (1)

Country Link
JP (1) JPS6412564A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0817267A1 (en) * 1994-03-11 1998-01-07 The Panda Project Semiconductor package having pins connected to inner layers of multilayer structure
EP1049163A1 (en) * 1999-04-27 2000-11-02 GLOTECH INC. Seoul Business Incubator Multiple line grid array package and a method for the manufacture thereof
US6384477B2 (en) 1997-04-26 2002-05-07 Glotech Inc. Multiple line grid array package

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0817267A1 (en) * 1994-03-11 1998-01-07 The Panda Project Semiconductor package having pins connected to inner layers of multilayer structure
US6384477B2 (en) 1997-04-26 2002-05-07 Glotech Inc. Multiple line grid array package
EP1049163A1 (en) * 1999-04-27 2000-11-02 GLOTECH INC. Seoul Business Incubator Multiple line grid array package and a method for the manufacture thereof

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