JPS6412354U - - Google Patents
Info
- Publication number
- JPS6412354U JPS6412354U JP10713387U JP10713387U JPS6412354U JP S6412354 U JPS6412354 U JP S6412354U JP 10713387 U JP10713387 U JP 10713387U JP 10713387 U JP10713387 U JP 10713387U JP S6412354 U JPS6412354 U JP S6412354U
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- relay
- transistor
- potential side
- vdc
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 5
- 238000009499 grossing Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Relay Circuits (AREA)
Description
第１図は本考案の一実施例によるリレー駆動回
路の回路図、第２図は一般的なリレーの周囲温度
と許容電圧、感動電圧及び保持電圧との相関関係
を示す特性図、第３図は本考案の同リレーに印加
される電源電圧の変化を説明する図、第４図は従
来の同回路図である。
３……整流器、４……平滑コンデンサ、５……
抵抗、６……第１のトランジスタ、７……定電圧
ダイオード、８……リレー、９……第２のトラン
ジスタ、１０……コンデンサ、１１……駆動信号
出力手段、１２……第３のトランジスタ、１３…
…遅延手段、ＶＤＣ……直流電圧、ａ，ｂ……出
力端、τ……遅延時間。
Fig. 1 is a circuit diagram of a relay drive circuit according to an embodiment of the present invention, Fig. 2 is a characteristic diagram showing the correlation between ambient temperature, allowable voltage, moving voltage and holding voltage of a general relay, and Fig. 3 4 is a diagram illustrating changes in the power supply voltage applied to the relay of the present invention, and FIG. 4 is a conventional circuit diagram of the same. 3... Rectifier, 4... Smoothing capacitor, 5...
Resistor, 6... First transistor, 7... Constant voltage diode, 8... Relay, 9... Second transistor, 10... Capacitor, 11... Drive signal output means, 12... Third transistor , 13...
...delay means, VDC...direct current voltage, a, b...output terminal, τ...delay time.
Claims (1)
サ４を介して発生する直流電源ＶＤＣの正電位側
に第１のトランジスタ６のコレクタ、負電位側に
コンデンサ１０を介してトランジスタ６のエミツ
タを接続し、また、前記電源ＶＤＣの正電位側に
抵抗５、負電位側に定電圧ダイオード７を介して
抵抗５を接続し、更に前記トランジスタ６とコン
デンサ１０との接続部及び前記電源ＶＤＣの負電
位側間にリレー８と第２のトランジスタ９とを接
続し、一方、前記電源ＶＤＣの正、負両電位側間
に駆動信号出力手段１１を接続するとともに、前
記第２のトランジスタ９のベースに前記出力手段
１１の出力端ａを接続し、また前記定電圧ダイオ
ード７のアノードと前記電源ＶＤＣの負電位側間
に前記リレー８に印加する電圧をリレー８の保持
電圧より多少高くして印加させる第３のトランジ
スタ１２を接続し、かつ、第３のトランジスタ１
２と前記第２のトランジスタ９の両ベース間に遅
延手段１３を接続したことを特徴とするリレー駆
動回路。 (2) 前記直流電源ＶＤＣの電圧は前記リレー８
の感動電圧よりも十分高くした実用新案登録請求
の範囲第１項記載のリレー駆動回路。 (3) 前記定電圧ダイオード７の電圧は前記リレ
ー８の許容電圧よりも十分低く、かつ、前記リレ
ー８の保持電圧に前記第１のトランジスタ６のベ
ース・エミツタ間の電圧を加えた電圧よりも高く
した実用新案登録請求の範囲第１項記載のリレー
駆動回路。 (4) 前記遅延手段１３の遅延時間τは、前記リ
レー８の動作応答時間よりも長くした実用新案登
録請求の範囲第１項記載のリレー駆動回路。[Claims for Utility Model Registration] (1) The collector of the first transistor 6 is connected to the positive potential side of the DC power supply VDC generated via the smoothing capacitor 4 connected to the output terminal of the rectifier 3, and the capacitor 10 is connected to the negative potential side. A resistor 5 is connected to the positive potential side of the power supply VDC, a resistor 5 is connected to the negative potential side of the power supply VDC via a constant voltage diode 7, and the transistor 6 and the capacitor 10 are connected through the resistor 5. A relay 8 and a second transistor 9 are connected between the power source VDC and the negative potential side of the power source VDC, and a drive signal output means 11 is connected between the positive and negative potential sides of the power source VDC. The output terminal a of the output means 11 is connected to the base of the transistor 9 of No. 2, and the voltage applied to the relay 8 between the anode of the voltage regulator diode 7 and the negative potential side of the power source VDC is set to the holding voltage of the relay 8. A third transistor 12 is connected to which the voltage is applied at a slightly higher level than the third transistor 1.
2 and the bases of the second transistor 9, a delay means 13 is connected between the bases of the relay drive circuit. (2) The voltage of the DC power supply VDC is the voltage of the relay 8.
2. The relay drive circuit according to claim 1, which is sufficiently higher than the touching voltage of the utility model. (3) The voltage of the constant voltage diode 7 is sufficiently lower than the permissible voltage of the relay 8, and is lower than the voltage obtained by adding the voltage between the base and emitter of the first transistor 6 to the holding voltage of the relay 8. A relay drive circuit according to claim 1 of the enhanced utility model registration claim. (4) The relay drive circuit according to claim 1, wherein the delay time τ of the delay means 13 is longer than the operation response time of the relay 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10713387U JPS6412354U (en) | 1987-07-13 | 1987-07-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10713387U JPS6412354U (en) | 1987-07-13 | 1987-07-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6412354U true JPS6412354U (en) | 1989-01-23 |
Family
ID=31341269
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10713387U Pending JPS6412354U (en) | 1987-07-13 | 1987-07-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6412354U (en) |
-
1987
- 1987-07-13 JP JP10713387U patent/JPS6412354U/ja active Pending
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