JPS62153580U - - Google Patents

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Publication number
JPS62153580U
JPS62153580U JP4099186U JP4099186U JPS62153580U JP S62153580 U JPS62153580 U JP S62153580U JP 4099186 U JP4099186 U JP 4099186U JP 4099186 U JP4099186 U JP 4099186U JP S62153580 U JPS62153580 U JP S62153580U
Authority
JP
Japan
Prior art keywords
emitter
transistors
bias
capacitor
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4099186U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP4099186U priority Critical patent/JPS62153580U/ja
Publication of JPS62153580U publication Critical patent/JPS62153580U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の第1実施例の回路図、第2図
は本考案の第2実施例の回路図、第3図は第1図
の回路を用いたフオーカスインジケータを示す回
路図、である。 (主要部分の符号の説明)、3……ダイオード
FIG. 1 is a circuit diagram of a first embodiment of the present invention, FIG. 2 is a circuit diagram of a second embodiment of the present invention, and FIG. 3 is a circuit diagram showing a focus indicator using the circuit of FIG. 1. It is. (Explanation of symbols of main parts), 3...Diode.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 2つのトランジスタのコレクタ同志及びエミツ
タ同志を接続すると共に、前記エミツタに抵抗を
接続し、前記エミツタに接続した抵抗と前記コレ
クタの間に適切な正負の電圧バイアスを加えたエ
ミツタホロワ回路において、前記2つのトランジ
スタのうちの一方のトランジスタのベースにコン
デンサを接続し、電気的交流信号を前記コンデン
サを介して前記一方のトランジスタのベースに与
えると共に、前記2つのトランジスタのベースに
抵抗を介してDCバイアスを与えるごとく構成さ
れた回路であつて、該DCバイアス値をトランジ
スタのVBE電圧を一致させる様ダイオードの順
方向電圧を用い、前記エミツタとグラウンドの間
に前記交流信号の半波整流信号を得ることを特徴
とする半波整流回路。
In an emitter follower circuit, the collectors and emitters of two transistors are connected together, a resistor is connected to the emitter, and an appropriate positive and negative voltage bias is applied between the resistor connected to the emitter and the collector. A capacitor is connected to the base of one of the transistors, and an electrical alternating current signal is applied to the base of the one transistor through the capacitor, and a DC bias is applied to the bases of the two transistors through resistors. The circuit is configured as follows, and is characterized in that a forward voltage of a diode is used to match the DC bias value with the VBE voltage of the transistor, and a half-wave rectified signal of the AC signal is obtained between the emitter and ground. Half-wave rectifier circuit.
JP4099186U 1986-03-20 1986-03-20 Pending JPS62153580U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4099186U JPS62153580U (en) 1986-03-20 1986-03-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4099186U JPS62153580U (en) 1986-03-20 1986-03-20

Publications (1)

Publication Number Publication Date
JPS62153580U true JPS62153580U (en) 1987-09-29

Family

ID=30855578

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4099186U Pending JPS62153580U (en) 1986-03-20 1986-03-20

Country Status (1)

Country Link
JP (1) JPS62153580U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51131206A (en) * 1975-05-10 1976-11-15 Nec Corp Signal rectifier circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51131206A (en) * 1975-05-10 1976-11-15 Nec Corp Signal rectifier circuit

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