JPS6284228U - - Google Patents

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Publication number
JPS6284228U
JPS6284228U JP17352285U JP17352285U JPS6284228U JP S6284228 U JPS6284228 U JP S6284228U JP 17352285 U JP17352285 U JP 17352285U JP 17352285 U JP17352285 U JP 17352285U JP S6284228 U JPS6284228 U JP S6284228U
Authority
JP
Japan
Prior art keywords
emitter
transistors
capacitor
transistor
controlling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17352285U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP17352285U priority Critical patent/JPS6284228U/ja
Publication of JPS6284228U publication Critical patent/JPS6284228U/ja
Pending legal-status Critical Current

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  • Networks Using Active Elements (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例の回路図、第2図、
第3図は本考案の別の実施例の回路図、第4図は
別の実施例のブロツク図である。 18,19…コンデンサ、17…可変容量ダイ
オード、20,21…抵抗。
Figure 1 is a circuit diagram of an embodiment of the present invention; Figure 2 is a circuit diagram of an embodiment of the present invention;
FIG. 3 is a circuit diagram of another embodiment of the present invention, and FIG. 4 is a block diagram of another embodiment. 18, 19... Capacitor, 17... Variable capacitance diode, 20, 21... Resistor.

Claims (1)

【実用新案登録請求の範囲】 1 第1及び第2のトランジスタと、第1及び第
2のトランジスタのそれぞれのコレクタに所定の
電圧を印加する手段と、第1のトランジスタのコ
レクタ出力により第2のトランジスタのベースを
制御する手段と、第2のトランジスタのコレクタ
出力により第1のトランジスタのベースを制御す
る手段と、第1及び第2のトランジスタのそれぞ
れのエミツタ間に接続されるコンデンサと、第1
及び第2のトランジスタのエミツタにそれぞれ接
続される電流源からなるエミツタ結合型マルチバ
イブレータにおいて、上記コンデンサを1個ある
いは複数の可変容量ダイオードとこの可変容量ダ
イオードと第1及び第2のトランジスタのエミツ
タとの間に接続されるコンデンサで構成し、上記
の可変容量ダイオードの容量を制御する手段を具
備したエミツタ結合型マルチバイブレータ。 2 特許請求範囲の第1項に記載のエミツタ結合
型マルチバイブレータにおいて第1及び第2のト
ランジスタのエミツタ電流を制御する手段を具備
したことを特徴とするエミツタ結合型マルチバイ
ブレータ。
[Claims for Utility Model Registration] 1. First and second transistors, means for applying a predetermined voltage to the respective collectors of the first and second transistors; means for controlling the base of the transistor; means for controlling the base of the first transistor by a collector output of the second transistor; a capacitor connected between respective emitters of the first and second transistors;
and an emitter-coupled multivibrator consisting of a current source connected to the emitter of the second transistor, respectively, in which the capacitor is connected to one or more variable capacitance diodes, and the variable capacitance diode and the emitters of the first and second transistors are connected to each other. An emitter-coupled multivibrator comprising a capacitor connected between the capacitor and the capacitor and having means for controlling the capacitance of the variable capacitance diode. 2. An emitter-coupled multivibrator according to claim 1, characterized in that the emitter-coupled multivibrator is equipped with means for controlling the emitter currents of the first and second transistors.
JP17352285U 1985-11-13 1985-11-13 Pending JPS6284228U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17352285U JPS6284228U (en) 1985-11-13 1985-11-13

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17352285U JPS6284228U (en) 1985-11-13 1985-11-13

Publications (1)

Publication Number Publication Date
JPS6284228U true JPS6284228U (en) 1987-05-29

Family

ID=31111058

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17352285U Pending JPS6284228U (en) 1985-11-13 1985-11-13

Country Status (1)

Country Link
JP (1) JPS6284228U (en)

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