JPS6412197B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a stepping motor drive control circuit.

Conventionally, a driven object driven by a stepping motor, such as the head of a disk device, uses an external head positioning signal (step signal) to control a positioning mechanism such as a stepping motor that drives the head, and moves the disk medium. Positioning of the head is being carried out. Therefore, if the step signal contains jitter (if the pulse interval of the step signal becomes shorter than the interval that the stepping motor can follow), the stepping motor will rotate according to the number of pulses of the step signal. As a result, the head could not be moved to the correct position.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a stepping motor drive control circuit that can rotate the stepping motor by a number of steps corresponding to the number of pulses of the step signal even when the step signal includes jitter. There is a particular thing.

According to the present invention, when the pulse interval of the step signal becomes less than a predetermined time, that is, when jitter occurs in the step signal, the pulse signal is supplied from the circuit that latches the step signal to the driving circuit of the stepping motor. A stepping motor drive control circuit is obtained, which is characterized in that the stepping motor is delayed by a predetermined time.

Next, the present invention will be described in detail with reference to the drawings showing one embodiment of the present invention.

In FIG. 1, a step signal 50 from an external control circuit 10 is input to a latch circuit 1, and the latched pulse signal is held until reset by an output signal 54 of a delay circuit 3. An output signal 51 from the latch circuit 1 is input to the delay circuit 3 via the AND circuit 2. Here, the delay circuit 3 is a circuit that sets the output for a certain period of time depending on the rise of the input signal 53. The output 54 of the delay circuit 3 serves as a reset signal to the latch circuit 1 as described above, and is also input to the delay circuit 4. The delay circuit 4 outputs a high signal all the time, but changes the output signal 52 to low for a certain period of time in consideration of the following speed of the motor to be controlled depending on the fall of the input signal 54.
This is a signal circuit. The output signal 52 of this delay circuit 4 is one input of the AND circuit 2,
Controls the opening and closing of this gate. The output signal 53 or 54 is given to the motor drive circuit 20 as a normalized step signal.

Next, the operation of this circuit will be explained with further reference to FIG. In this embodiment, an example will be described in which a stepping motor that can follow pulse signals with a maximum interval of 25 msec is controlled.

The step signal 50 from the control circuit 10 outputs step pulses at 3 msec intervals during normal operation, but due to malfunction or the like, jitter (a phenomenon in which the pulse intervals are not equal) occurs in this signal. In the illustrated example, the interval from the first pulse 50a to the second pulse 50b is shortened to 3 msec or less.

The pulse 50a of the step signal 50 is latched in the circuit 1 and inputted to the delay circuit 3 via the gate 2 which is kept open by the signal from the delay circuit 4. The delay circuit 3 provides the motor drive circuit 20 with a signal 54 that maintains the high state of the signal 53 for a predetermined time (10 μsec). As a result, the rotation of a stepping motor (not shown) connected to the drive circuit 20 is advanced by one step.

The output signal 54 of the delay circuit 3 resets the high state of the latch circuit 1 to the low state at its falling edge, and is also applied to the delay circuit 4, so that its high
Set the state to LOW. The duration of the LOW state of delay circuit 4 is the maximum tracking time of the stepping motor.
It is set to 2.8 msec, which is an intermediate value between 2.5 msec and 3 msec, which is the normal pulse generation interval of the step signal 50.

Next, two of the step signals 50 are output at intervals shorter than the following time of the stepping motor.
Since the numbered pulse 50b is latched by the latch circuit 1, its output line 51 is in a high state. However, this High signal is the output 5 of the delay circuit 4.
Since the gate 2 is closed while the signal 53 is in the LOW state, the signal 53 is in the LOW state and is not applied to the delay circuit 3. When the delay circuit 4 calculates a certain period of time (2.8 msec) from the pulse sending of the delay circuit 3, its output 52 becomes High again and the gate 2 is opened. As a result, the High signal latched in circuit 1 is applied to delay circuit 3. Therefore, the pulse 50b is sent to the delay circuit 3.
As a result, the drive circuit 20 can send out pulses at intervals that can be followed by the stepping motor.

Incidentally, assuming that the step signal 50 sends out pulses at normal pulse intervals (3 msec) after the pulse 50c, the pulse signal 5 given to the drive circuit 20
The delay time for the step signal 50 of No. 4 gradually decreases, and after a few pulses, it completely returns to the state before jitter occurred.

Therefore, if this drive control circuit is used in a head positioning circuit of a disk device, the head can be positioned without error even in response to a step signal that exceeds the follow-up speed.

As explained above, the present invention has the advantage that by supplying pulses to the drive circuit through the delay circuit, the motor can be driven normally despite jitter.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure is an operation timing diagram of the circuit shown in FIG. 1. 1...Latch circuit, 2...AND circuit, 3, 4
...Delay circuit.

Claims (1)

[Claims] 1. A latching means for latching a first step signal having a number of pulses corresponding to the amount of movement of the stepping motor; and a gate means for generating a second step signal using the output of the latching means as one input;
a delay means for delaying the output of the gate means for a predetermined time; a drive means for receiving the output of the delay means and driving the step motor by an amount corresponding to the number of pulses of the second step signal; and timer means for closing the gate means for a predetermined time from a pulse input to the stepper motor, the latch means being reset by a pulse input to the drive means. circuit.