JPH0824439B2 - Stepping motor drive - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a flexible disk drive (hereinafter,
FDD device) is related to the stepping motor drive device used.

[Prior Art] FIG. 4 is a block diagram showing a conventional stepping motor driving device of an FDD device. In the figure, (1) is a step pulse signal input terminal, (2) is a direction switching signal input terminal, (3) is a pulse train generation circuit, (4) is a second pulse switching circuit, (5) is a step pulse interval detection circuit, (6) is a direction switching detection circuit,
(7) is a stepping motor drive circuit, (8) is a stepping motor, and (9) is a system FDD controller (hereinafter simply referred to as a system) for connecting an FDD.

FIG. 5 is a timing chart for explaining an example of the operation of the stepping motor drive device of the conventional FDD device of FIG. In the figure, (10) is an input step pulse train input from the system (9), (11) is an input direction signal input from the system (9), and (12).
Is a direction switching reset signal output from the direction switching detection circuit (6) when the direction switching detection circuit (6) receives the input direction signal (11) and the direction signal is switched. In this example, the L level is reset. . (13) is a step pulse interval detection signal output from the step pulse interval detection circuit (5) upon receiving the input step pulse train (10) and the direction switching reset signal (12). In this example, the input step pulse train (10) When the signal interval exceeds the predetermined range, the H level is output, and when the signal interval is within the predetermined range, the L level is output.
(14) receives the step pulse interval detection signal (13), and receives from the second pulse switching circuit (4) a fixed time T ₁ or T ₂ input step pulse train depending on whether the level of the signal (13) is L or H. Second step pulse train output after (10), (15) receives the input step pulse train (10) and the second step pulse train (14) in the pulse train generation circuit (3), and the internal step in which the two pulse trains are combined A pulse train, (16) is a stepping motor phase output that is output from the pulse train generating circuit (3) to the stepping motor drive circuit (7) along the internal step pulse train (15). A phase → B phase → C phase → D When the phases are output in the order of phase → A phase, the stepping motor (8) driven thereby moves the read / write head of the FDD from the outer circumference to the inner circumference of the disk-shaped recording medium, D phase → C phase → B phase → A
When the output is in the order of phase → D phase, it is to be moved from the inner circumference to the outer circumference. (17) is the first step pulse, (1
8) is the second step pulse.

FIG. 6 shows a return-to-movement for moving the FDD read / write head from the innermost circumference of the recording medium to the outermost track 0.
A timing chart when a zero instruction (hereinafter referred to as RTZ instruction) is performed is shown. In the figure, (19) is a track 0 signal output when the read / write head is located at track 0, and the read / write head is located at track 0. Sometimes L level is output.

Next, the operation will be described with reference to FIGS. 4 and 5. First, when the input step pulse train (10) is input from the system (9) through the step pulse input terminal (1), the pulse interval is detected by the step pulse interval detection circuit (5), and the pulse interval is set. A step pulse interval detection signal (13) of a level that depends on whether it is within or outside a predetermined range is output, and is delayed from the second pulse switching circuit (4) by a time input step pulse train (10) corresponding to the level of the signal (13). Second pulse train (1
4) is output. This second step pulse train (1
4) and the input step pulse train (10) are combined by the pulse train generation circuit (3) to generate the internal step pulse train (15), which is tuned to this internal step pulse train (15) and is determined by the input direction signal (11). The stepping motor phase output (16) is output and amplified by the stepping motor drive circuit (7) to drive the stepping motor (8).

If the pulse interval Ts ₁ of the first step pulse (17) of the input step pulse train (10) is within the set time Ts (Ts> Ts ₁ ), the step pulse interval detection signal (1
The output of 3) is L level, and the second step pulse train (14) output from the second pulse switching circuit (4).
The second step pulse (18) is generated after the first step pulse (17) for the first predetermined time T ₁ shorter than Ts ₁ . Next, the pulse interval of the input step pulse train (10) is
When it becomes larger than Ts ₁ (Ts <Ts ₂ ) and exceeds a predetermined range, it is detected by the step pulse interval detection circuit (5), and the step pulse interval detection signal (13) changes from L level to H level. Second pulse switching circuit (4) accordingly
The time delay of the second step pulse (18) from the first step pulse (17) is longer than the first predetermined time T ₁ by Ts ₂
The second predetermined time T ₂ is shorter. The first step pulse (17) has the next pulse interval of the input step pulse train (10).
When returning to within the predetermined range Ts, the step pulse interval detection signal (13) becomes L level again, and the first step pulse (1
The time interval between 7) and the second step pulse (18) is T ₁ . Next, when the input direction signal (11) from the system (9) changes from the H level to the L level, the direction switching reset signal (12) from the direction switching circuit (6) changes the step pulse interval detection circuit (5). ), And when the reset signal (12) is generated, even if the pulse interval of the input step pulse train (10) is outside the set time Ts, it is considered to be within that range, and an L level step pulse is detected. The signal (13) is output.

By the way, in the system (9), the integrated circuit (hereinafter referred to as FDC) for controlling the FDD is generally 8 inches or 5.25 inches among the types of recording medium size, 8 inches, 5.25 inches and 3.5 inches. It was made as an FDC for FDD, so to use it as an FDC for 3.5-inch FDD,
It is necessary to change the interface logic and change the output timing. For example, in case of 8 inch and 5.25 inch FDD, the number of tracks is 77, the maximum number of step pulses required for RTZ command is 76, and 8 inch and 5.
The initial FDC made for the 25-inch FDD outputs only 77 shots including the step pulse when the RTZ command is included.
On the other hand, in the 3.5-inch FDD, the number of tracks is 80, and the maximum number of step pulses required for the RTZ command is 79. Therefore, FDC for 8 inch and 5.25 inch FDD can be converted to 3.5 inch FDD
, And from the innermost circumference of the recording medium to RT as shown in FIG.
When executing the Z command, the head is not returning to track 0 even if the _77th step pulse T ₇₇ is output after the RTZ command, so it is detected that the track 0 signal (19) is not output and the repeat RTZ command is executed. Is generated, and the driving of the head in the outer peripheral direction is continued. Therefore, this step pulse T ₇₇
And the next step pulse T ₇₈ , the time T _W is
Of detection, for RTZ re-instruction, longer than the pulse interval T _R of the continuous 77 shots of the step pulse at the time of RTZ instruction (T _R <T _W) becomes.
If T _R is shorter than the set time Ts and T _W is longer than Ts, the second pulse of the step pulse T ₇₇ with the pulse interval T _R is ₁ hour later, and the second pulse of the step pulse T ₇₈ with the pulse interval T _W. The pulse is T ₂ hours later, and the next step pulse
The second pulse of T ₇₉ is _one hour after T. in this way,
The time of the second pulse becomes T ₂ only after T _W , the time Ts ₇₈ from the second pulse of step pulse T ₇₈ to the next step pulse T ₇₉ becomes extremely short, and the stepping motor phase output (16) at that time Since the next phase A is output before the stepping motor (8) can follow the phase B output, the response of the stepping motor is further delayed, and the track 0 signal (19) outputs the L level in the next step. The stepping motor phase output for the step pulse of T ₈₀ occurs after the input of the pulse T ₈₀ , and the head moves to the outer peripheral side from the determined outermost track 0.

[Problems to be Solved by the Invention] Since the conventional FDD stepping motor driving device is configured as described above, the stepping motor cannot follow the abrupt change of the step pulse interval, and the movement to the instructed track is defective. Occurs, or when re-instructing the RTZ instruction, it is necessary to increase the waiting time or lengthen the step pulse interval.

In order to prevent such a defective movement of the head,
It was possible to fix the generation time of the second pulse to output the second pulse at half the minimum pulse interval of the step pulse, but if the second pulse generation time is fixed, the step pulse with a long interval is input. At this time, since the time of each stepping motor phase output is not constant, the movement of the stepping motor becomes unstable and noise is generated. Although it can be prevented by adjusting the track 0 sensor that detects the track 0 signal (19), there is a problem that the adjustment range is narrowed and the mass productivity is lowered.

The present invention has been made in order to solve the above problems, and a stepping motor follows a rapid change in the step pulse interval and prevents a defective movement to an instructed track, thereby achieving high speed and reliability. An object is to obtain a high stepping motor drive device.

[Means for Solving the Problems] A stepping motor drive device according to the present invention is provided when a step pulse interval detection circuit continuously changes a signal interval of step pulse signals from a small range to a large range over a predetermined range. Is configured such that the output signal changes only when the signal interval is continuously maintained after the change.

[Operation] In the stepping motor drive device according to the present invention, the generation timing of the second step pulse does not change immediately even if the signal interval of the continuously input step pulse signals changes from a small range to a large range over a predetermined range. Instead, the timing of generation of the second step pulse is delayed only when the long signal interval is continuously maintained. Therefore, it does not respond to the instantaneous increase in the first step pulse interval, and the step pulse interval does not change suddenly.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing chart for explaining an example of the operation, and FIG. 3 is a timing chart for explaining an operation at the RTZ instruction in this embodiment. Is. In the figure, (1) is a step pulse signal input terminal, (2) is a direction switching signal input terminal, (3) is a pulse train generation circuit, and (4).
Is a second pulse switching circuit, (5) is a step pulse interval detection circuit, (6) is a direction switching detection circuit,
(7) is a stepping motor drive circuit, (8) is a stepping motor, (9) is a system, (10) is an input step pulse train, (11) is an input direction signal, and (12).
Is a direction switching reset signal, (13) is a step pulse interval detection signal, (14) is a second step pulse train, (15) is an internal step pulse train, (16) is a stepping motor phase output, (17) is a first step pulse, (1
8) is the second step pulse (19) is the track 0 signal,
The above is the configuration of the step pulse interval detection circuit (5) and the step pulse interval detection signal (13) output from the circuit.
The same as the conventional example shown in FIGS. 4 to 6 except for. That is, the step pulse interval detection circuit (5) of this embodiment
Performs the same operation as the step pulse interval detection circuit (5) of the conventional example, and the same first step pulse interval detection signal (2) as the step pulse interval detection signal (13) of the conventional example.
First step pulse interval detection circuit (20) that outputs 3)
And a second step pulse interval detection circuit (21) that outputs a second step pulse interval detection signal (24) whose level changes with a delay of one step pulse from the first step pulse interval detection circuit (20), Both of these detection signals (20),
It is composed of a logical product circuit (22) which takes the logical product of (21) and outputs it as a step pulse interval detection signal (13).

Next, the operation will be described with reference to FIGS. 1 and 2. First, when the input step pulse train (10) is input from the system (9) through the step pulse input terminal (1), the pulse interval is detected by the first step pulse interval detection circuit (20) and the pulse interval is set. If the first step pulse interval detection signal (23) of the L level if it is within the predetermined range, and the H level if it is out of the range is input at the end of the detected pulse interval, the first step pulse (17) is input. The second step pulse interval detection circuit (21) also detects the pulse interval of the input step pulse train (10). If the pulse interval is within a predetermined range, it is at the L level, and if it is outside the range, it is at the H level. The 2-step pulse interval detection signal (24) is output at the time of inputting the first step pulse (17) next to the first step pulse (17) at the end of the detected pulse interval. That is, the first and second step pulse interval detection circuits (20) and (21) deviate from the first step pulse train (10) by one step interval,
The second step pulse interval detection signals (23) and (24) are output. Both these step pulse interval detection signals (2
3) and (24) are input to the AND circuit (22), and their logical product, that is, both step pulse interval detection signals (23),
When either one of (24) is L level, an L level signal is output from the step pulse interval detection circuit (5) as a step pulse interval detection signal (13) when both are H level. Therefore, the step pulse interval detection signal (13) of the logical product of these two signals becomes the H level only when the long pulse interval Ts ₂ exceeding the predetermined range continues for two pulse intervals or more. This step pulse interval detection signal (13) is input to the second pulse switching circuit (4). From this circuit (4), when the step pulse interval detection signal (13) is at L level, the input step pulse train (10) outputs T ₁ , when H level
A second step pulse train (14) delayed by T ₂ is output. The second step pulse train (14) and the input step pulse train (10) are combined by the pulse train generation circuit (3) to generate an internal step pulse train (15), which is synchronized with the internal step pulse train (15) and the input direction signal (11). ) Outputs a stepping motor phase output (16) in a determined direction, which is amplified by the stepping motor drive circuit (7) to drive the stepping motor (8).

If the pulse interval Ts ₁ of the first first step pulse (17) of the input step pulse train (10) is within the set time Ts (Ts> Ts ₁ ), the first step pulse interval detection circuit ( This is detected in 20) and the first step pulse interval detection signal (23) becomes L level, so the output of the step pulse interval detection signal (13) is also L level and the second step output from the second pulse switching circuit (4). The second step pulse (18) of the pulse train (14) occurs after the first step pulse (17) for a first predetermined time T ₁ shorter than Ts ₁ . Next, when the pulse interval of the input step pulse train (10) becomes larger than Ts ₁ (Ts <Ts ₂ ) and exceeds the predetermined range, it is detected by the first step pulse interval detection circuit (20), and the first step pulse is detected. Interval detection signal (23) is L
Change from level to H level. However, at this time, in the second step pulse interval detection circuit (21), the previous pulse interval Ts ₁
Is detected and the second step pulse interval detection signal (24) is at L level, the step pulse interval detection signal (13) which is the logical product of these two signals (23) and (24) remains at L level. The second step pulse (18) of the second step pulse train (14) output from the second pulse switching circuit (4) still occurs after the first step pulse (17) for the first predetermined time T ₁ . When the pulse interval of the input step pulse train (10) returns within the predetermined range Ts at the next first step pulse (17), the first step pulse interval detection signal (23) becomes L level again, and the second step pulse interval detection signal Even if (24) becomes H level with a delay of one step pulse interval, the step pulse interval detection signal (13) becomes L level.
At the level, the second step pulse (18) still occurs after the first step pulse (17) for the first predetermined time T ₁ . That is, even if the input step pulse train (10) exceeds the predetermined range Ts by one step pulse interval, the generation timing of the second step pulse train (14) does not change. However, if the pulse interval Ts _{2 that} is longer than the 2 step pulse interval is maintained, the second step pulse interval detection signal (24) also becomes H level from the second pulse, and the step pulse interval detection signal (13) becomes H level. . Accordingly, the time delay of the second step pulse (18) from the second pulse switching circuit (4) from the first step pulse (17) becomes the second predetermined time T ₂ which is longer than the first predetermined time T ₁ . The operation when the output level of the input direction signal (11) changes is similar to that of the conventional example, and the description thereof is omitted.

Next, considering the case where the RTZ command is executed from the innermost circumference of the recording medium with reference to FIG. 3, the step pulse interval at the RTZ command is shorter than the set time T ₂ , and the 77th step pulse T ₇₇ and the next step. Even if the pulse interval T _W between the pulses T ₇₈ is longer than the set time Ts and the pulse interval up to the next step pulse T ₇₈ becomes shorter than Ts, step pulses with a pulse interval longer than Ts are not input continuously. , The first and second step pulse interval detection signals (23) and (24) do not become H level, and the step pulse interval detection signal (13)
Is still at the L level and the first of the second step pulse
The delay time T ₁ from the step pulse is constant and does not change.
Therefore, the time of each of the A, B, C, and D phases of the stepping motor becomes extremely short, and the phenomenon that the stepping motor cannot follow will not occur.

In the above embodiment, the step pulse interval detection circuit that outputs the logical product of the first and second step pulse interval detection signals deviated by one step pulse is shown. When the signal interval changes from a small value to a large value over a predetermined range, another circuit configuration may be used as long as the output signal changes only when the signal interval is continuously maintained after the change.

[Effects of the Invention] As described above, according to the present invention, when the step pulse interval detection circuit continuously changes the signal interval of step pulse signals from a small range to a large range over a predetermined range, Since the output signal is configured to change only when the signal interval is continuously maintained, it does not respond to a sudden increase in the first step pulse interval, and an extremely short stepping motor output phase occurs. In other words, the stepping motor can be easily followed, and the stepping motor driving device with high reliability and high speed can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG.
FIG. 3 is a timing chart for explaining an example of the operation, FIG. 3 is a timing chart for explaining the operation at the RTZ instruction in this embodiment, and FIG. 4 is a block line showing a conventional stepping motor driving device of an FDD device. 5 and 5 are timing charts for explaining an example of the operation of the apparatus of FIG. 4, and FIG. 6 is a timing chart for explaining the operation of the apparatus of FIG. 4 at the RTZ instruction. In the figure, (3) is a pulse train generation circuit, (4) is a second pulse switching circuit, (5) is a step pulse interval detection circuit, (6) is a direction switching detection circuit, (7) is a stepping motor drive circuit, and (8). ) Is a stepping motor, (20) is the first step pulse interval detection circuit, (2
1) is a second step pulse interval detection circuit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A pulse train generation circuit that generates a pulse train for two step feeds and outputs the pulse train to a stepping motor drive circuit by inputting one step pulse signal, and a signal interval between the step pulse signals that are continuously input. A step pulse interval detection circuit that detects and changes the output signal in response to a change in the signal interval exceeding a predetermined range, and a second step of the pulse train generation circuit in response to an output change of the step pulse interval detection circuit. In a stepping motor driving device having a second pulse switching circuit for switching timing, when the signal interval of the step pulse signals continuously input to the step pulse interval detection circuit changes from small to large over a predetermined range. Is characterized in that the output signal changes only when the signal interval is continuously maintained after the change. Stepping motor driving device according to.