JPH07117841B2 - Pulse width modulation type drive - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse width modulation type driving device for driving various loads such as an actuator, a motor, a speaker and an electromagnet.

2. Description of the Related Art Generally, in order to efficiently drive a load such as an actuator, a motor, a speaker, and an electromagnet, a pulse width modulation type drive device that suppresses power loss in the drive device by driving the load by switching operation is preferable. Used.
A conventional pulse width modulation type driving device generally has a structure as shown in FIG. The configuration will be described below with reference to FIGS. 9 and 10. However, FIG. 10 is a timing chart showing the operation of the conventional pulse width modulation type driving device.

In FIG. 9, reference numeral 91 is a drive timing generation means for generating a drive timing command B according to the drive input signal A, and 92 is an output means for driving the load 93 by the drive timing command B from the drive timing generation means 91. is there. When the drive input signal A is input to the drive timing generation means 91, the drive timing generation means 91 outputs a drive timing command B to the output means 92 according to the level of the drive input signal A, and the output means 92 is As shown in Figure 10,
The load 93 is driven by outputting an output signal having a pulse width corresponding to the drive input signal level. At this time, since the output means 92 performs the switching operation, the power loss of the pulse width modulation type driving device can be suppressed to be low and the driving can be performed efficiently.

However, in the conventional pulse width modulation type driving device shown in FIG. 9, as shown in FIG. 11 (b), the rising time and the falling time of the output signal of the output means 92 are , The pulse area is not equal to the pulse area of the output signal in the ideal case where the rise time and the fall time are zero, resulting in an error, as shown in FIG. 11 (a). As the pulse width of the output signal becomes smaller, its influence cannot be ignored.

Further, as shown in FIG. 11 (c), the delay time from when the output means 92 receives the drive timing command B for raising the output signal from the drive timing generation means 91 until the output signal starts to rise, and the output means 92 Is the drive timing generation means
Even when the delay time from when the output signal falling drive timing command is received from 91 until the output signal starts falling is different, the pulse area is equal to the pulse width of the ideal output signal in Fig. 11 (a). However, this tendency becomes more remarkable as the pulse width becomes smaller, and no pulse is output when the drive input signal level is near zero. That is, there is a dead zone (a region in which no pulse is output even if the drive input signal A is not zero) near the drive input signal level of zero, which adversely affects when driving a load such as an actuator, a motor, or a speaker. Will end up.

The present invention solves the above-mentioned conventional problems, and causes a pulse area and an error of an ideal output signal due to the difference between the rising time and the falling time of the output signal from the output means,
In addition, since the delay time until the output signal from the output means starts to rise and the delay time until the output signal starts to fall are not equal to the pulse width of the ideal output signal, a pulse is output especially when the drive input signal level is near zero. It is an object of the present invention to provide a pulse width modulation type driving device capable of preventing such problems as not being performed.

Means for Solving the Problems In order to solve the above problems, a pulse width modulation type driving device of the present invention comprises first and second output means for outputting a pulsed output signal, and the first and second outputs. Drive timing generation means for giving drive timing commands for in-phase output and anti-phase output to the means, and the first and second output means between the output of the first output means and the output of the second output means. The load connected to be driven by the difference component of the output of the drive circuit is driven only when the pulsed output signals of the phases output from the first and second output means are in reverse phase, and the drive timing generation means drives the load. In-phase of the first and second output means by giving a drive timing command of in-phase output and anti-phase output according to the drive input signal input to the drive timing generation means to the first and second output means. Also, the output pulse width of the reverse phase is increased and decreased successively.

In addition to the above configuration, in the pulse width modulation type driving device of the present invention, when the drive input signal input to the drive timing generation means indicates a positive value, at least the output signal of the first output means rises and then the The signal of the second output means rises with a delay, or the output signal of the first output means falls with a delay after the second output means falls, and the signal is input to the drive timing generation means. When the drive input signal is negative, at least after the output signal of the second output means rises, the first output means
Signal of the output means rises with a delay, or the output signal of the first output means falls and then the output of the second output means falls with a delay, and is input to the drive timing generation means. When the drive input signal represents zero, the output signal of the first output means and the output signal of the second output means rise at the same time, and fall at the same time, so that the load is divided into the first and second loads.
It is configured to be driven by the difference component of the two-phase pulsed output signals output from the output means.

Further, the drive timing generation means in the pulse width modulation type drive device of the present invention counts the number of pulses of the reference clock signal by the number corresponding to the drive input signal, and the time required for the counting is used to output the first output means. The drive timing command for shifting the rising or falling timings of the output signal and the output signal of the second output means is generated.

With the above configuration, a load is connected between the two output means of the first and second output means, and a difference component between the two-phase pulsed output signals output from the first and second output means is used. Drive the load. That is, the load is not driven when the output signals of the first and second output means are in phase, and the load is driven when the output signals of the first and second output means are in opposite phase. Therefore, in accordance with the drive input signal, the drive timing generation means outputs the drive timing command so that the rising or falling timing of at least the output signal of the first output means and the output signal of the second output means is deviated. As a result, the load is driven by the difference in the timing.

At that time, in the pulse width modulation type driving device of the present invention, the load is driven by the rising time difference or the falling time difference of the output signals of the first and second output means. Rise time and fall time, or delay time from when the output means receives the drive timing command for raising the output signal from the drive timing generation means until the output signal starts to rise and when the output means lowers the output signal from the drive timing generation means Even if the delay time from the receipt of the drive timing command from the start to the fall of the output signal is different, the rise time and fall time of the output signal are about the same in the first output means and the second output means. Also, it is output after receiving the drive timing command for raising the output signal from the drive timing generation means. The delay time until the signal starts to rise and the delay time from when the output means receives the drive timing command of the output signal falling from the drive timing generation means to when the output signal starts to fall are also the first output means and the second output. As long as the same means is used, the difference signal waveform between the output signal of the first output means and the output signal of the second output means, which represents the actual driving state of the load, is not adversely affected and accurate even when the pulse width is small. The load is driven by the pulse area,
At this time, for example, an actuator, a motor,
There is no dead zone that adversely affects when driving a load such as a speaker.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a pulse width modulation type driving device which is an embodiment of the present invention. In FIG. 1, 11
Is a drive timing generation means for generating a drive timing command according to the drive input signal A, and 12 and 13 are output means for driving the load 14 by the drive timing command B1 from the drive timing generation means 11. The load 14 is an output means
12 and the output means 13 are driven by the difference component of the two-phase pulse-shaped output signals, that is,
When the output signals of the output means 12 and the output means 13 are in phase, they are not driven, and when the output signals of the output means 12 and the output means 13 are in opposite phase, they are driven. Therefore, according to the drive input signal, the drive timing command means causes the drive timing instruction means to shift the rising or falling timing of the output signal of the output means 12 and the output signal of the output means 13 from each other.
By outputting B1, the load 14 is driven by the difference in the timing. The load 14 is placed between the output of the output means 12 and the output of the output means 13 so as to be driven in the positive direction when the output signal of the output means 12 is at a high level and the output signal of the output means 13 is at a low level. It is connected.

Drive input signal and output signal of output means 12 and output means 13
The relationship of the output signals of is shown in FIG. That is, the second
When the drive input signal A is positive and the output signals of the output means 12 and the output means 13 immediately before are low level as shown in the point a, first, the output signal of the output means 12 rises to drive. The output signal of the output means 13 rises with a delay corresponding to the level of the input signal A. At this time, load 14
Is (output signal of output means 12)-(output means 13) of FIG.
The output signal of the output means 12 is driven in the positive direction from the rise of the output signal of the output means 12 to the rise of the output signal of the output means 13. Also, FIG. 2b
When the drive input signal A is positive and the output signals of the output means 12 and the output means 13 immediately before are at a high level like the point, the output signal of the output means 13 first falls and the level of the drive input signal. Then, the output signal of the output means 12 falls with a delay corresponding to. At this time, the load 14 is (output signal of output means 12)-(output signal of output means 13) of FIG.
As shown by the waveform, the signal is driven in the positive direction from the fall of the output signal of the output means 13 to the fall of the output signal of the output means 12.

Next, when the drive input signal is negative and the output means 12 and the output signal of the output means 12 immediately before are at a low level as shown in FIG. 2c, the output signal of the output means 13 rises first, The output signal of the output means 12 rises with a time delay according to the level of the drive input signal. At this time, the load 14 outputs the output signal of the output means 12 after the output signal of the output means 13 rises, as shown by the waveform of (output signal of output means 12)-(output signal of output means 13) in FIG. It is driven in the negative direction until the output signal rises. Further, when the drive input signal is negative and the output signals of the output means 12 and the output means 13 immediately before are high level as shown at point d in FIG. 2, first, the output signal of the output means 12 falls. The output signal of the output means 13 falls with a time delay according to the level of the drive input signal. At this time, the load 14 is (output means 12 in FIG.
Output signal)-(output signal of output means 13), as shown by the waveform of (output signal of output means 13), it is driven in the negative direction from the time when the output signal of output means 12 falls until the output of output means 13 falls. .

Further, when the drive input signal is zero and the output signals of the output means 12 and the output means 13 immediately before are low level as in the point e of FIG. 2, the output signal of the output means 12 and the output means 13 are output.
The output signals of rise at the same time. The load 14 is (output signal of output means 12)-(output signal of output means 13) in FIG.
Is not driven as shown by the waveform. Also, FIG. 2f
When the drive input signal is zero as in the case of dot and the output signals of the output means 12 and the output means 13 immediately before are at high level, the output signal of the output means 12 and the output signal of the output means 13 rise simultaneously. Go down. At this time, the load 14 is not driven as shown by the waveform of (output signal of output means 12)-(output signal of output means 13) in FIG.

As described above, in the pulse width modulation type driving device of this embodiment, the load 14 is driven by the difference in the rising timing or the falling timing of the output signals of the output means 12 and the output means 13. Therefore, as shown in FIG. 3 (b), even if the output signals of the output means 12 and the output means 13 have different rising times and falling times, the rising time and the falling time of the output signal are output by the output means 12. And the output means 13 have the same degree, the waveform of the difference signal between the output signal of the output means 12 and the output signal of the output means 13, which represents the actual driving state of the load 14, is shown in FIG. Output signal of means 12)-(output signal of output means 13)
The rising time and the falling time of the waveform are equalized, and the influence of the difference between the rising time and the falling time of the output signals of the output means 12 and the output means 13 is eliminated. In particular, when the rising characteristic and the falling characteristic of the output signal of the output means 12 and the output signal of the output means 13 can be approximated by a straight line, it is the waveform of the difference signal between the output signal of the output means 12 and the output signal of the output means 13. In FIG. 3B, (output means 12
Output signal)-(output signal of output means 13), pulse means of waveform, output means of output means 12 and output means of output means 13 The waveform of the difference signal between the output signal of 12 and the output signal of the output means 13 is shown in FIG.
Output signal)-(output signal of output means 13) has the same pulse area, and the load can be driven with an accurate pulse area even when the pulse width is small.

Similarly, the delay time from the output means 12 and the output means 13 receiving the drive timing command B1 for raising the output signal from the drive timing generation means 11 to the start of the output signal, and the output means 12 and the output means 13 are Drive timing command for output signal fall from drive timing generation means 11
Even if the delay time from the reception of B1 to the start of the output signal is different, the delay time from the reception of the drive timing command B1 from the drive timing generation means 11 to the start of the output signal If the delay time from when the drive timing command B1 for lowering the output signal is received from the drive timing generation means to when the output signal starts to fall is similar between the output means 12 and the output means 13, the actual load drive The waveform of the difference signal between the output signal of the output means 12 and the output signal of the output means 13 representing the state, (output signal of the output means 12)-(output means 13) in FIG. 3 (c).
Output signal of the output means 12 and the output means
13 is a delay time from when the drive timing generation means 11 receives the drive timing command for raising the output signal to when the output signal starts to rise, and the output means 12 and the output time 13 are set by the drive timing generation means 11 to decrease the output signal. The effect of the difference from the delay time from when the drive timing command B1 is received until the output signal starts to fall is eliminated, and there is no dead zone that adversely affects the driving of loads such as actuators, motors, and speakers. Especially output means
When the rising characteristics and the falling characteristics of the output signal of 12 and the output signal of the output means 13 can be approximated by a straight line, the waveform of the difference signal between the output signal of the output means 12 and the output signal of the output means 13 is shown in FIG. c) (output signal of output means 12)-
The pulse area of (the waveform of the output signal of the output means 13), the output signal of the output means 12, and the output signal of the output means 12 in the ideal case where the rise time and the fall time of the output signal of the output means 13 are zero. The waveform of the difference signal of the output signal of the output means 13 (the output signal of the output means 12) of FIG.
The pulse areas of the waveform of (the output signal of the output means 13) become equal, and the load 14 can be driven with an accurate pulse area even when the pulse width is small.

As described above, even when the rising time and the falling time of the output signal of the output means are different, or until the output signal starts to rise after receiving the drive timing command of the output signal rising from the drive timing generation means Even if the delay time of the output signal is different from the delay time from when the output means receives the drive timing command for the output signal falling from the drive timing generation means until the output signal starts to fall, especially when the pulse width is small. It is possible to drive a load with an accurate pulse area, and there is no dead zone that adversely affects when driving a load such as an actuator, a motor, and a speaker.

Here, FIG. 4 shows a structural example of the drive timing generation means 11. In FIG. 4, 41 is a preset up / down counter, 42 is a NOR gate, 43, 44, 47, 48 and 49 are D flip-flops, and 45 and 46 are D flip-flops with set / reset.

The operation of one configuration example of the drive timing generation means 11 of FIG. 4 having the above configuration will be described below.

First, the drive input signal represented by the two's complement representation is the preset input P of the preset up / down counter 41.
(LSB) to P (MSB), and since the preset enable signal ▲ ▼ is 0 at this time, the preset up / down counter 41 is preset. Then, when the start signal is raised to 1, the output Q of the D flip-flop 43 rises in synchronization with the reference clock, the preset enable signal ▲ ▼ becomes 1, and the preset up / down counter 41 starts counting. At this time, since the up count / down count switching input U / of the preset up / down counter 41 becomes the value of the most significant digit of the preset drive input signal A, the preset up / down counter 41 has a positive drive input signal. When is down, it counts down, and when it is negative, it counts up. When the preset up / down counter 41 counts the reference clock signal by the number corresponding to the drive input signal A, all the outputs Q (LSB) to Q (MSB) of the preset up / down counter 41 become 0 and the output of the NOR gate 42 becomes 0. Change from 1 to 1 and count enable input ▲
▼ becomes 1 and up / down counter with preset 41
Stops counting. That is, the start signal rises to 1 and the D flip-flop is synchronized with the reference clock.
The output of the NOR gate 42 rises to 1 with a time delay according to the drive input signal after the output Q of 43 rises. The drive timing command B1 given to the output means 12 and the output means 13 is generated using the time delay at this time.

Now, if the drive input signal A is positive and the output signals of the output means 12 and the output means 13 immediately before are at a low level as shown in the point a of FIG. 2, the output means 12 and the output means immediately before are output.
The output Q of the flip-flop 48 which holds the level of the output signal of 13 is 0 (the inverted output is 1), and when the start signal rises to 1, the output Q of the D flip-flop 43 rises in synchronization with the reference clock, At the rising edge, the inverted output of the flip-flop 44 becomes 1, and the output Q of the D flip-flop 45 with set / reset rises to 1. Then, when the output of the NOR gate 42 rises to 1 after a time delay according to the drive input signal, all the inputs of the NAND gate connected to the set input of the set / reset D flip-flop 46 become 1 and set / reset. The set input of the attached D flip-flop 46 becomes 0, and the output Q of the set / reset D flip-flop 46 is set to 1. D flip-flop with set / reset 45 and D with set / reset
The output Q of the flip-flop 46 is synchronized with the reference clock signal by the flip-flops 47 and 48 and given to the output means 12 and the output means 13 as a drive timing command.

Similarly, when the drive input signal is positive and the output signals of the output means 12 and the output means 13 immediately before are high level as in the point b of FIG. 2, the output means 12 and the output means 13 immediately before are output.
The output Q of the flip-flop 48 which holds the level of the output signal of 1 is 1. When the start signal rises to 1, the output Q of the D flip-flop 43 rises in synchronization with the reference clock, and the rising edge thereof causes the flip-flop 44 to rise. The inverting output becomes 1, and the output Q of the D flip-flop with set / reset 46 falls to 0.
Then, after a time delay according to the drive input signal, NOR gate 4
When the output of 2 rises to 1, NA connected to the reset input of the D flip-flop 45 with set / reset
All inputs of ND gate become 1 and D with set / reset
The reset input of the flip-flop 45 becomes 0, and the output Q of the D flip-flop 45 with set / reset is reset to 0. D flip-flop with set / reset 45 and D flip-flop with set / reset
The output Q of 46 is synchronized with the reference clock signal by the flip-flops 47 and 48 and given to the output means 12 and the output means 13 as a drive timing command.

Further, when the drive input signal is negative and the output signals of the output means 12 and the output means 13 immediately before are at a low level as in the point c of FIG. 2, the output means 12 and the output means 13 immediately before are output.
The output Q of the flip-flop 48 that holds the level of the output signal of 0 is 0 (the inverted output is 1), and the start signal is 1
When it rises, the output Q of the D flip-flop 43 rises in synchronization with the reference clock, and the rising edge causes the output Q of the flip-flop 44 to become 1 and the output Q of the D flip-flop with set / reset 46 rises to 1. Then, after a time delay according to the drive input signal
When the output of the NOR gate 42 rises to 1, all the inputs of the NAND gate connected to the set input of the set / reset D flip-flop 45 become 1 and the set input of the set / reset D flip-flop 45 becomes 0. The output of the D flip-flop 45 with set / reset is set to 1. The outputs Q of the D flip-flop with set / reset 45 and the D flip-flop with set / reset 46 are synchronized with the reference clock signal by the flip-flops 47 and 48, and given to the output means 12 and the output means 13 as a drive timing command.

Similarly, when the drive input signal is negative and the output signals of the output means 12 and the output means 13 immediately before are high level as in the point d of FIG. 2, the outputs of the output means 12 and the output means 13 immediately before are output. The output Q of the flip-flop 48 that holds the signal level is 1, and when the start signal rises to 1, the output Q of the D flip-flop 43 rises in synchronization with the reference clock, and the flip-flop is driven by its rising edge.
Output Q of 44 becomes 1 and D with set / reset
The output of the flip-flop 45 falls to 0. continue,
If the output of the NOR gate 42 rises to 1 after a time delay corresponding to the drive input signal, all the inputs of the NAND gate connected to the reset input of the D flip-flop 46 with set / reset become 1 and the D flip-flop with set / reset becomes The reset input of the flip-flop 46 becomes 0, and the output Q of the D flip-flop with set / reset 46 is reset to 0. D flip-flop with set / reset 45
The output Q of the D flip-flop 46 with set / reset is synchronized with the reference clock signal by the flip-flops 47 and 48, and the output means 12 is provided as a drive timing command.
And output means 13.

Further, when the drive input signal is zero and the output signals of the output means 12 and 13 immediately before are at a low level as shown in the point e of FIG. 2, the output means 12 and output means 13 immediately before are output.
The output Q of the flip-flop 48 that holds the level of the output signal of 0 is 0 (the inverted output is 1), and the start signal is 1
When it rises, the output Q of the D flip-flop 43 rises in synchronization with the reference clock, the inverted output of the flip-flop 44 becomes 1 by the rising edge, and the output Q of the D flip-flop 45 with set / reset rises to 1. At the same time, the output of the NOR gate 42 rises to 1 and all the inputs of the NAND gate connected to the set input of the D flip-flop 46 with set / reset are 1
The set input of the D flip-flop with set / reset 46 becomes 0, and the output Q of the D flip-flop with set / reset 46 is set to 1. The outputs Q of the D flip-flop with set / reset 45 and the D flip-flop with set / reset 46 are synchronized with the reference clock signal by the flip-flops 47 and 48, and given to the output means 12 and the output means 13 as a drive timing command.

Similarly, when the drive input signal is zero and the output signals of the output means 12 and the output means 13 immediately before are at a high level as shown in point f of FIG. 2, the output means 12 and the output means 13 immediately before are output.
The output Q of the flip-flop 48 which holds the level of the output signal of 1 is 1. When the start signal rises to 1, the output Q of the D flip-flop 43 rises in synchronization with the reference clock, and the rising edge thereof causes the flip-flop 44 to rise. The inverting output becomes 1, and the output Q of the D flip-flop with set / reset 46 falls to 0. At the same time, the output of the NOR gate 42 rises to 1 and all the inputs of the NAND gate connected to the reset input of the D flip-flop 45 with set / reset become 1 and the reset input of the D flip-flop 45 with set / reset is 0.
Then, the output Q of the set / reset D flip-flop 45 is reset to zero. D with set / reset
The outputs Q of the flip-flop 45 and the D flip-flop with set / reset 46 are synchronized with the reference clock signal by the flip-flops 47 and 48, and given to the output means 12 and the output means 13 as a drive timing command.

Next, another embodiment of the present invention will be described with reference to the drawings.

FIG. 5 is a block diagram showing the configuration of a pulse width modulation type driving device which is another embodiment of the present invention. In FIG. 5, 51 is a drive timing command B2 according to the drive input signal A.
Drive timing generation means for generating
Is the drive timing command from the drive timing generation means 51
It is an output means for driving the load 54 by B2. Load 54
It is driven by the difference component of the two-phase pulsed output signals output from the output means 52 and the output means 53, that is, when the output signals of the output means 52 and the output means 53 are in phase, they are not driven, It is driven when the output signals of the output means 52 and the output means 53 have opposite phases. Therefore, the drive timing command is output by the drive timing generation means so as to shift the rising or falling timing of the output signal of the output means 52 and the output signal of the output means 53 in accordance with the drive input signal. The load is driven by the amount of. The load 54 is connected between the output of the output means 52 and the output of the output means 53 so that the load 54 is driven in the positive direction when the output signal of the output means 52 is at a high level and the output signal of the output means 53 is at a low level. Has been done.

Drive input signal A and output signal of output means 52 and output means
The relationship of the output signals of 53 is shown in FIG. That is, when the drive input signal A is positive as at point g in FIG.
First, the output signal of the output means 52 and the output signal of the output means 53 rise simultaneously, and then, after the output signal of the output means 53 falls, the output means 52 of the output means 52 is delayed by a time corresponding to the level of the drive input signal. The output signal falls. At this time, the load 54 is (the output signal of the output means 52) of FIG.
As indicated by the waveform of (output signal of output means 53), the drive is performed in the positive direction from the time when the output signal of the output means 53 falls until the time when the output signal of the output means 52 falls.

Next, if the drive input signal A is negative, as at point h in FIG. 6, the output signal of the output means 52 and the output means 53 are first output.
Simultaneously rises, then the output signal of the output means 52 falls, and then the output signal of the output means 53 falls with a time delay corresponding to the level of the drive input signal. At this time, the load 54 is (the output signal of the output means 52) of FIG.
As indicated by the waveform of (output signal of output means 53), the output signal of output means 52 is driven in the negative direction from the time it falls until the output signal of output means 53 falls.

Further, when the drive input signal A is zero as at the point i in FIG. 6, first, the output signal of the output means 52 and the output means are outputted.
The output signal of 53 rises at the same time, and subsequently, the output signal of the output means 52 and the output signal of the output means 53 fall at the same time. Therefore, the load 54 is not driven as shown by the waveform of (output signal of output means 52)-(output signal of output means 53) in FIG. In this way, the load is driven by the difference in the falling timings of the output signals of the output means 52 and the output means 53. Therefore, as shown in FIG. 7B, even when the output signals of the output means 52 and the output means 53 have different rising times and falling times, the rising time and the falling time of the output signal are output by the output means 52. And the output means 53 have the same degree, the waveform of the difference signal between the output signal of the output means 52 and the output signal of the output means 53 showing the actual driving state of the load 54 is shown in FIG. The output signal of the means 52)-(output signal of the output means 53) has the same rise time and fall time, and the difference between the rise time and the fall time of the output signals of the output means 52 and the output means 53 There is no impact. In particular, when the rising characteristic and the falling characteristic of the output signal of the output means 52 and the output signal of the output means 53 can be approximated by a straight line, it is the waveform of the difference signal between the output signal of the output means 52 and the output signal of the output means 53. 7 (b) (output signal of output means 52)-
The pulse area of the waveform of (the output signal of the output means 53), the output signal of the output means 52, and the output signal of the output means 52 in the ideal case where the rise time and the fall time of the output signal of the output means 53 are zero The waveform of the difference signal of the output signal of the output means 53 (the output signal of the output means 52) of FIG.
The pulse areas of the waveform of (the output signal of the output means 53) become equal, and the load can be driven with an accurate pulse area even when the pulse width is small.

Similarly, the delay time from when the output means 52 and the output means 53 receive the drive timing command B2 for raising the output signal from the drive timing generation means 51 until the output signal starts to rise, and the output means 52 and the output means 53 are Even if the delay time from the reception of the drive timing command B2 for falling the output signal from the drive timing generation means 51 to the start of the output signal is different, the drive timing command for rising the output signal is generated by the drive timing generation means. The delay time from the reception of B2 to the start of the output signal and the delay time from the reception of the drive timing instruction B2 from the drive timing generation means to the start of the output signal from the drive timing generation means to the output means 52 and the output means If it is about the same as 53, the output means that shows the actual driving condition of the load.
In the waveform of (output signal of output means 52)-(output signal of output means 53) of FIG. 7 (c), which is the waveform of the difference signal between the output signal of 52 and the output signal of output means 53, output means 52 and output The delay time from when the means 53 receives the drive timing command B2 for raising the output signal from the drive timing generation means 51 to when the output signal starts to rise, and the output means 52 and the output means 53 raise the output signal from the drive timing generation means 51. The influence of the difference between the delay time from receiving the drive timing command B2 for lowering until the output signal starts to fall is eliminated, and there is no dead zone that adversely affects when driving the load 54 such as the actuator, motor, and speaker. . In particular, when the rising characteristic and the falling characteristic of the output signal of the output means 52 and the output signal of the output means 53 can be approximated by a straight line, it is the waveform of the difference signal between the output signal of the output means 52 and the output signal of the output means 53. The pulse area of the waveform of (output signal of output means 52)-(output signal of output means 53) in FIG. 7C, the rise time and fall time of the output signal of output means 52 and the output signal of output means 53. Is a waveform of a difference signal between the output signal of the output means 52 and the output signal of the output means 53 in the ideal case where is zero (output signal of the output means 52)-(output means 53). The pulse area of the waveform of the output signal) becomes equal, and the load can be driven with an accurate pulse area even when the pulse width is small.

In this way, even if the rising time and the falling time of the output signal of the output means are different,
The delay time from the drive timing generation means 51 receives the drive timing command B2 for the output signals 52 and 53 to the start of the output signal rise, and the output means 52 and 53 lowers the output signals from the drive timing generation means 51. Even if the delay time from receiving the drive timing command B2 of until the output signal starts falling is different, and even when the pulse width is small, the load can be driven with an accurate pulse area,
In addition, there is no dead zone that adversely affects the driving of loads such as actuators, motors and speakers.

Note that FIG. 8 shows an example of the configuration of the drive timing generation means 51. In FIG. 8, 81 is a preset up / down counter, 82 is a NOR gate, 83, 85, 88 and 89 are D flip-flops, 84 is a monostable multivibrator, and 86 and 87 are D flip-flops with reset.

The operation of one configuration example of the drive timing generation means of FIG. 8 having the above configuration will be described below.

First, the drive input signal A represented by the two's complement representation is the preset input P of the preset up / down counter 81.
(LSB) to P (MSB). Then, when the start signal is raised to 1, the output Q of the D flip-flop 83 rises in synchronization with the reference clock and triggers the monostable multivibrator 84. At this time, the inverted output of the monostable multivibrator 84 falls to 0, the preset enable input ▲ ▼ of the preset up / down counter 81 becomes 0, and the drive input signal A is preset in the preset up / down counter 81. A fixed time after the monostable multivibrator 84 is triggered, the inverted output of the monostable multivibrator 84 rises, the preset enable signal ▲ ▼ becomes 1, and the preset up / down counter 81 starts counting. At this time, the up / down counter with preset 81
Up / down count switching input U /
Is the most significant digit of the preset drive input signal A, the preset up / down counter 81 counts down when the drive input signal is positive and counts up when the drive input signal is negative. After that, when the preset up / down counter 81 counts the reference clock signal by the number corresponding to the drive input signal A, all the outputs Q (LSB) to Q (MSB) of the preset up / down counter 81 become 0, and the output of the NOR gate 82. Changes from 0 to 1, the count enable input ▲ ▼ becomes 1, and the preset up / down counter 81 stops counting. That is, after the inverted output of the monostable multivibrator 84 rises to 1, the NOR gate 8 is delayed by a time corresponding to the drive input signal A.
The output of 2 falls to 0. Drive timing command B2 given to output means 52 and output means 53 using the time delay at this time
To generate.

For example, when the drive input signal A is positive as at point g in FIG. 6, when the start signal rises to 1, the output Q of the D flip-flop 83 rises in synchronization with the reference clock, and the monostable multivibrator 84 Trigger. Further, the output Q of the D flip-flop 83 with reset rises to 1 by the rising of the output Q of the D flip-flop 83. The inverted output of the monostable multivibrator 84 rises at 1 after a certain time has elapsed, the preset enable signal ▲ ▼ becomes 1, and the preset up / down counter 81 starts counting. At the same time, the output Q (MS
Since B) is 0, the inverted output of the D flip-flop 85 becomes 1 and the reset input of the D flip-flop with reset 86 becomes 0, and the D flip-flop with reset 86
Is reset. Then, when the preset up / down counter 81 counts the reference clock signal by the number corresponding to the drive input signal A, all the outputs Q (LSB) to Q (MSB) of the preset up / down counter 81 become 0.
When the output of the NOR gate 82 changes from 0 to 1, the reset input of the D flip-flop with reset 87 becomes 0, and the output Q of the D flip-flop with reset 87 is reset to 0. The outputs Q of the D flip-flop with reset 86 and the D flip-flop with reset 87 are synchronized with the reference clock signal by the D flip-flops 88 and 89, and given to the output means 52 and the output means 53 as the drive timing command B2.

When the drive input signal A is negative as at point h in FIG. 6, when the start signal rises to 1, the output Q of the D flip-flop 83 rises in synchronization with the reference clock, and the monostable multivibrator 84 Trigger. Also D
As the output Q of the flip-flop 83 rises, the output Q of the D flip-flops 86 and 87 with reset rises to 1. The inverted output of the monostable multivibrator 84 rises at 1 after a certain time has elapsed, the preset enable signal ▲ ▼ becomes 1, and the preset up / down counter 81 starts counting. At the same time, since the output Q (MSB) of the preset up / down counter 81 is 1, the output Q of the D flip-flop 85 is 1, the reset input of the reset D flip-flop 87 is 0, and the reset D flip-flop 87 is Will be reset. Next, when the preset up / down counter 81 counts the reference clock signal by the number corresponding to the drive input signal A, the preset up / down counter 81
Outputs Q (LSB) to Q (MSB) are all 0 and NOR gate 8
When the output of 2 changes from 0 to 1, the reset input of the D flip-flop with reset 86 becomes 0, and the output Q of the D flip-flop with reset 86 is reset to 0.
The outputs Q of the D flip-flop with reset 86 and the D flip-flop with reset 87 are synchronized with the reference clock signal by the flip-flops 88 and 89, and given to the output means 52 and the output means 53 as the drive timing command B2.

Further, when the drive input signal is zero as at point i in FIG. 6, when the start signal rises to 1, the output Q of the D flip-flop 83 rises in synchronization with the reference clock, and the monostable multivibrator 84 is turned on. Trigger. Also,
As the output Q of the D flip-flop 83 rises, the output Q of the D flip-flops with reset 86 and 87 rises to 1. When the inverted output of the monostable multivibrator 84 rises to 1 after a certain period of time, the outputs Q of the preset up / down counter 81 are all 0, so the reset inputs of the D flip-flops 86 and 87 with reset become 0 and the D with reset D Flip-flops 86 and 87
Is reset. D flip-flop with reset 86
Also, the output Q of the D flip-flop with reset 87 is synchronized with the reference clock signal by the flip-flops 88 and 89 and given to the output means 52 and the output means 53 as a drive timing command.

In another embodiment, the output signal of the output means 52 and the output signal of the output means 53 are raised at the same time, and the load is driven by the difference in the falling timings of the output signals of the output means 52 and the output means 53. The load may be driven by the difference in the rising timings of the output signals of the output means 52 and the output means 53, and the output signals of the output means 52 and the output means 53 may fall simultaneously. Therefore, in both the one embodiment and the other embodiment of the present invention, the load can be driven by the difference between the rising timings of the output signals of the output means 12 and 52 and the output means 13 and 53 or the difference of the falling timings. It is possible.

In addition, an optical disc device that records or reproduces at least information by irradiating a recording medium with laser light,
A focus actuator used for focus control for focusing laser light, a tracking actuator used for tracking control for causing laser light to follow a target track on the recording medium, or a transfer actuator for transferring an optical head equipped with the focus actuator and the tracking actuator. Alternatively, it can be used to drive at least one load of a magnetic field applying device that applies a magnetic field to a recording medium.

As described above, according to the present invention, a load is connected between the first and second output means, and the drive timing generation means outputs at least the output signal of the first output means in accordance with the drive input signal. And the second output means output the output signals of the output signals from the first and second output means such that the rising or falling timings of the output signals are different from each other. Since the load is driven by the time difference, the rising time and the falling time of the output signal of the output means, or until the output signal starts to rise after the output timing of the output means receives the drive timing command of the output signal from the drive timing generation means Delay time and the output means receives the drive timing command of the output signal falling from the drive timing generation means Even if the delay time until the output signal starts to fall is different, the rise time and fall time of the output signal are about the same in the first output means and the second output means, and the output means is driven. The delay time from the receipt of the drive timing command for raising the output signal from the timing generation means until the start of the output signal and the rise of the output signal after the output means receives the drive timing instruction for the fall of the output signal from the drive timing generation means If the delay time until the start of falling is similar between the first output means and the second output means, the output signal of the first output means and the output of the second output means that represent the actual driving state of the load. The difference signal waveform of the signal is not adversely affected, and the load can be driven with an accurate pulse area even when the pulse width is small.
There is no dead zone that adversely affects the driving of loads such as actuators, motors, and speakers.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a pulse width modulation type driving device according to an embodiment of the present invention, FIG. 2 is a timing diagram showing the operation of each main part in FIG. 1, and FIGS. FIG. 3C is an input / output waveform diagram of each main part in the same pulse width modulation type driving device, FIG. 3A is an ideal case diagram, and FIG. 3B is an output signal of the output means 12 and FIG. 3C shows a case where the rising time and the falling time of the output signal of the output means 13 are different. In FIG. 3C, the output means 12 and the output means 13 receive the drive timing command for raising the output signal from the drive timing generation means 11. And the delay time from the start of the output signal to the output means 12 and the output means 13 from the drive timing generation means 11 receiving the drive timing command for the output signal to fall When is different FIG. 4 is a circuit diagram showing an example of the structure of the drive timing generating means 11 of FIG. 1, and FIG. 5 is a block diagram showing the structure of a pulse width modulation type driving device of another embodiment of the present invention. FIG. 6 is a timing chart showing the operation of each main portion in FIG. 5, and FIGS. 7 (a) to 7 (c) are input / output waveform charts of each main portion in the pulse width modulation type driving device. Figure (a) is an ideal case, Figure 7 (b)
Shows the case where the rising time and the falling time of the output signal of the output means 52 and the output signal of the output means 53 are different. In FIG. 7 (c), the output means 52 and the output means 53 output signals from the drive timing generation means 51. The delay time from the receipt of the drive timing command for start-up until the start of the output signal, and the output means 52, the output means 53 outputs the output signal from the drive timing generation means 51 after receiving the drive timing instruction for the fall FIG. 8 is a circuit diagram showing a configuration example of the drive timing generation means 51 of FIG. 5, and FIG. 9 is a conventional pulse width modulation type drive. Block diagram showing the configuration of the device,
FIG. 10 is a timing chart showing the operation of each main portion in FIG. 9, FIGS. 11 (a) to 11 (c) are input / output waveform charts in the pulse width modulation type driving device, and FIG. 11 (a) is Fig. 11 (b) is an ideal case, Fig. 11 (b) shows a case where the rising time and the falling time of the output signal of the output means 92 are different, and Fig. 11 (c) shows the output means 92 from the drive timing generation means 91. The delay time from when the drive timing command for raising the output signal is received until the output signal starts to rise, and the output means 92
FIG. 6 is a diagram in the case where the delay time from when the drive timing command for driving the output signal to fall is received from the drive timing generation means 91 to when the output signal starts to fall is different. 11 ... Drive timing generation means, 12 ... Output means, 13 ...
Output means, 14 load, 41 up / down counter with preset, 42 NOR gate, 43 D flip-flop, 44 D flip-flop, 45 set
D flip-flop with reset, 46 ... D flip-flop with set / reset, 47 ... D flip-flop, 48 ... D flip-flop, 49 ... D flip-flop, 51 ... drive timing generation means, 52 ... output Means 53 output means 54 load 81 up-down counter with preset 82 NOR gate 83 D
Flip-flop, 84 ... Monostable multivibrator,
85 ... D flip-flop, 86 ... D flip-flop with reset, 87 ... D flip-flop with reset, 88 ... D flip-flop, 89 ... D flip-flop.

Claims (3)

[Claims] 1. A first and second output means for outputting a pulsed output signal, and a drive timing generation means for giving a drive timing command for in-phase output and anti-phase output to the first and second output means. A load connected between the output of the first output means and the output of the second output means so as to be driven by the difference component of the outputs of the first and second output means. 2 output from 2 output means
The drive timing command is driven only when the phase pulse output signal is in the reverse phase, and the drive timing command of the in-phase output and the anti-phase output corresponding to the drive input signal input to the drive timing generation means is output by the first drive timing generation means. And a pulse width modulation type driving device configured to sequentially increase or decrease the in-phase and anti-phase output pulse widths of the first and second output means by giving the same to the second output means. 2. When the drive input signal input to the drive timing generation means is positive, at least the output signal of the first output means rises and then the signal of the second output means rises with a delay, or If the output signal of the first output means rises with a delay after the second output means rises, and the drive input signal input to the drive timing generation means is negative, then at least the second output means. After the output signal of the output means rises, the signal of the first output means rises with a delay, or after the output signal of the first output means falls, the second signal
When the output of the output means of FIG. 2 falls with a delay and the drive input signal input to the drive timing generation means represents zero, the output signal of the first output means and the output signal of the second output means of When the output signals rise at the same time and fall at the same time, the load is brought into the first and second sections.
2. The pulse width modulation type drive device according to claim 1, wherein the pulse width modulation type drive device is configured to be driven by a difference component of two-phase pulsed output signals output from the output means. 3. The drive timing generation means counts the number of pulses of the reference clock signal by the number corresponding to the drive input signal, and the time required for the counting is used to output the output signal of the first output means and the second output. 3. The pulse width modulation type driving device according to claim 2, wherein the driving timing command for shifting the rising or falling timing of the output signal of the means is generated.