JPS6412098B2 - - Google Patents
Info
- Publication number
- JPS6412098B2 JPS6412098B2 JP24765383A JP24765383A JPS6412098B2 JP S6412098 B2 JPS6412098 B2 JP S6412098B2 JP 24765383 A JP24765383 A JP 24765383A JP 24765383 A JP24765383 A JP 24765383A JP S6412098 B2 JPS6412098 B2 JP S6412098B2
- Authority
- JP
- Japan
- Prior art keywords
- cap
- substrate
- semiconductor device
- package
- cooling mechanism
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 28
- 238000001816 cooling Methods 0.000 claims description 26
- 239000004065 semiconductor Substances 0.000 claims description 22
- 238000007789 sealing Methods 0.000 claims description 17
- 239000000919 ceramic Substances 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 9
- 229910010293 ceramic material Inorganic materials 0.000 claims description 7
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- KZHJGOXRZJKJNY-UHFFFAOYSA-N dioxosilane;oxo(oxoalumanyloxy)alumane Chemical compound O=[Si]=O.O=[Si]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O KZHJGOXRZJKJNY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052863 mullite Inorganic materials 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229920000049 Carbon (fiber) Polymers 0.000 claims description 2
- 239000004917 carbon fiber Substances 0.000 claims description 2
- 239000002131 composite material Substances 0.000 claims description 2
- AHADSRNLHOHMQK-UHFFFAOYSA-N methylidenecopper Chemical compound [Cu].[C] AHADSRNLHOHMQK-UHFFFAOYSA-N 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
〔発明の利用分野〕
本発明は、複数個の半導体デバイスを実装した
パツケージを封止し冷却するパツケージの封止冷
却機構に関する。
〔発明の背景〕
複数の半導体デバイスを実装したパツケージの
従来の封止冷却機構の一例として、第１図にその
断面を示す。この機構は、半導体デバイス３を搭
載したセラミツク基板１と、該セラミツク基板１
にロー付けされ、かつ該セラミツク基板１の端部
を越えて外方にのびた環状フランジ２と、該フラ
ンジに係合するキヤツプ４と、該フランジ２と該
キヤツプ間の環状ガスケツト６と、該フランジ２
と該キヤツプ４の係合状態を維持するためのクラ
ンプ部材５により封止体を形成する。上記半導体
デバイス３から熱を取り除くために上記キヤツプ
４に冷却手段７が取り付けられている。上記機構
では、キヤツプ４とセラミツク基板１は別体をな
しているから、キヤツプ４の熱膨張係数をセラミ
ツク基板１の熱膨張係数に整合させなくても良
い。そのためキヤツプ４の材料として、たとえば
アルミニウムのような高い熱伝導率を有する材料
が使用できる。しかし上記機構では熱膨張係数の
異なる部材を互に強固に固定するため、封止のた
めのフランジ２やキヤツプ４やクランプ部材５の
部分が上記セラミツク基板１の外に突き出て、パ
ツケージの占有面積が大きくなる。このため、パ
ツケージ相互間の配線が長くなり、複数のパツケ
ージからなるシステム全体の信号遅延が増大する
という欠点があつた。
また、他の従来の封止冷却機構として、半導体
デバイスを搭載したセラミツク基板と、セラミツ
ク基板の半導体デバイス搭載面を覆い、かつこの
搭載面の端部にて基板接合されたセラミツク基板
と同材質のセラミツクで作つたキヤツプとで封止
体を形成しているものが知られている。半導体デ
バイスから熱を取り除くためにキヤツプに冷却手
段が取り付けられている。上記機構では、セラミ
ツク基板とキヤツプの熱膨張係数の不整合に基づ
く問題はないが、セラミツク材はあまり高い熱伝
導率を持たないので、高い冷却性能を得にくいと
いう欠点があつた。
〔発明の目的〕
本発明は上述の点にかんがみてなされたもの
で、封止のための部分を極小化し、かつ高い冷却
性能を持つ半導体デバイス用のパツケージ封止冷
却機構を提供することを目的とする。
〔発明の概要〕
上述の目的を達成するため、本発明は、デバイ
スが搭載されるセラミツク材料からなる基板に、
この基板の熱膨脹係数と等しいかほゞ整合する熱
膨脹係数及び該基板より高い熱伝導率を有する高
熱伝導性セラミツク材料よりなるキヤツプを半田
封止したことを特徴とするものである。
〔発明の実施例〕
以下、本発明の実施例を図面に基づいて説明す
る。
第２図は本発明の一実施例をなすパツケージの
封止冷却機構を示す一部切断斜視図であり、第３
図はその断面図である。
複数個の半導体デバイス１３がフリツプチツプ
によつて、焼成された多層ムライトセラミツク材
からなる基板１１の上表面に電気的、物理的にハ
ンダ付けで接続される。基板１１の基板裏表面に
はパツケージが外部と電気的に接続するための
Ｉ／Ｏピン１６がロー付けされている。基板１１
には半導体デバイス３とＩ／Ｏピン１６が電気的
に相互に接続されるための表面層および内層配線
を有している。半導体デバイス１３を封止するた
めに炭化シリコン（SiC）を材料とするキヤツプ
１２が基板１１に固着されている。キヤツプ１２
には、キヤツプ１２の内面と半導体デバイス１３
の間にあつて、半導体デバイス１３の発熱をキヤ
ツプ１２に伝えるための熱伝導手段１４と、キヤ
ツプ１２に集められた熱を取り除くための冷却手
段として水冷ジヤケツト１５が取り付けられてい
る。１７と１８は各々水冷ジヤケツト１５の水の
入出口である。
上記キヤツプ１２の材質は銅―炭素繊維複合材
料
[Field of Application of the Invention] The present invention relates to a package sealing and cooling mechanism for sealing and cooling a package in which a plurality of semiconductor devices are mounted. [Background of the Invention] FIG. 1 shows a cross section of an example of a conventional sealed cooling mechanism for a package in which a plurality of semiconductor devices are mounted. This mechanism includes a ceramic substrate 1 on which a semiconductor device 3 is mounted, and a ceramic substrate 1 on which a semiconductor device 3 is mounted.
An annular flange 2 soldered to the ceramic substrate 1 and extending outward beyond the edge of the ceramic substrate 1, a cap 4 that engages with the flange, an annular gasket 6 between the flange 2 and the cap, and the flange 2
A sealing body is formed by a clamp member 5 for maintaining the engaged state of the cap 4. Cooling means 7 are attached to the cap 4 to remove heat from the semiconductor device 3. In the above mechanism, since the cap 4 and the ceramic substrate 1 are separate bodies, it is not necessary to match the thermal expansion coefficient of the cap 4 to that of the ceramic substrate 1. Therefore, as the material of the cap 4, a material having high thermal conductivity such as aluminum can be used. However, in the above mechanism, since members with different coefficients of thermal expansion are firmly fixed to each other, the flange 2, cap 4, and clamp member 5 for sealing protrude outside the ceramic substrate 1, reducing the area occupied by the package. becomes larger. This has the disadvantage that the wiring between the packages becomes long and the signal delay of the entire system consisting of a plurality of packages increases. In addition, as another conventional sealing cooling mechanism, a ceramic substrate on which a semiconductor device is mounted, and a ceramic substrate made of the same material as the ceramic substrate that covers the semiconductor device mounting surface of the ceramic substrate and is bonded to the substrate at the edge of this mounting surface. It is known to form a sealed body with a cap made of ceramic. Cooling means are attached to the cap to remove heat from the semiconductor device. Although the above mechanism does not have problems due to mismatching of the coefficients of thermal expansion between the ceramic substrate and the cap, it has the disadvantage that it is difficult to obtain high cooling performance because the ceramic material does not have very high thermal conductivity. [Object of the Invention] The present invention has been made in view of the above points, and an object of the present invention is to provide a package sealing cooling mechanism for semiconductor devices that minimizes the sealing portion and has high cooling performance. shall be. [Summary of the Invention] In order to achieve the above-mentioned object, the present invention provides a substrate made of a ceramic material on which a device is mounted.
The device is characterized in that a cap made of a highly thermally conductive ceramic material having a thermal expansion coefficient equal to or substantially matching that of the substrate and a thermal conductivity higher than that of the substrate is soldered and sealed. [Embodiments of the Invention] Hereinafter, embodiments of the present invention will be described based on the drawings. FIG. 2 is a partially cutaway perspective view showing a sealing cooling mechanism for a package according to an embodiment of the present invention;
The figure is a sectional view thereof. A plurality of semiconductor devices 13 are electrically and physically connected by flip chips to the upper surface of a substrate 11 made of a fired multilayer mullite ceramic material by soldering. I/O pins 16 are soldered to the back surface of the substrate 11 for electrically connecting the package to the outside. Board 11
has a surface layer and inner layer wiring for electrically interconnecting the semiconductor device 3 and the I/O pin 16. A cap 12 made of silicon carbide (SiC) is fixed to the substrate 11 for sealing the semiconductor device 13 . cap 12
The inner surface of the cap 12 and the semiconductor device 13 are shown in FIG.
In between, a heat conduction means 14 for transmitting the heat generated by the semiconductor device 13 to the cap 12, and a water cooling jacket 15 as a cooling means for removing the heat collected in the cap 12 are attached. 17 and 18 are water inlet and outlet ports of the water cooling jacket 15, respectively. The material of the cap 12 is copper-carbon fiber composite material.
【Cu―CFRM（以下単にCu―CFRMと記す）】
でもよく、その場合は基板１１の材料はアルミナ
セラミツクでもよい。
上記封止冷却機構において、半導体デバイス１
３により発生する熱は熱伝導手段１４を介してキ
ヤツプ１２に集められ、キヤツプ１２に集められ
た熱は水冷ジヤケツト１５で熱交換され、外部に
排出される。シリコン、ムライトセラミツク、ア
ルミナセラミツク、炭化シリコン、Cu―CFRM
の熱膨張係数と伝導率は表１に示すような関係に
なつている。[Cu-CFRM (hereinafter simply referred to as Cu-CFRM)]
In that case, the material of the substrate 11 may be alumina ceramic. In the above sealing cooling mechanism, the semiconductor device 1
The heat generated by the cap 3 is collected in the cap 12 via the heat conduction means 14, and the heat collected in the cap 12 is exchanged with the water cooling jacket 15 and discharged to the outside. Silicon, mullite ceramic, alumina ceramic, silicon carbide, Cu-CFRM
The thermal expansion coefficient and conductivity of are in the relationship shown in Table 1.
【表】【table】
以上説明したように、本発明によれば、複数個
の半導体デバイスを実装したパツケージに高い冷
却性能を与えることが可能になり、かつパツケー
ジ間の信号遅延が減少し、複数のパツケージから
なるシステムの性能向上が可能となるという優れ
た効果が得られる。また、本発明においては、キ
ヤツプを基板と同じセラミツク材料とすること
で、両者の熱膨脹率を近づけており、これによ
り、キヤツプと基板の封止部におけるズレが少な
くなり、半田封止でも十分ズレを吸収できる程度
におさえられる効果がある。
As explained above, according to the present invention, it is possible to provide high cooling performance to a package mounting a plurality of semiconductor devices, reduce signal delay between packages, and improve the efficiency of a system consisting of a plurality of packages. An excellent effect is obtained in that performance can be improved. In addition, in the present invention, by making the cap and the substrate the same ceramic material, the coefficients of thermal expansion of the two are made close to each other. This reduces misalignment at the sealing portion between the cap and the substrate, and even solder sealing can sufficiently prevent misalignment. It has the effect of suppressing it to the extent that it can be absorbed.
第１図は従来のパツケージの封止冷却機構を示
す断面図、第２図、第３図は本発明の一実施例を
なすパツケージの封止冷却機構を示す図で、第２
図は一部切断斜視図、第３図は断面図、第４図は
本発明の他の実施例をなすパツケージの封止冷却
機構の断面図である。
１１，１２…基板、１２，２２…キヤツプ、１
３，２３…半導体デバイス、１４…熱伝導手段、
２４…熱伝導ペースト、１５…水冷ジヤケツト、
１６，２６…Ｉ／Ｏピン。
FIG. 1 is a sectional view showing a conventional package sealing cooling mechanism, and FIGS. 2 and 3 are views showing a package sealing cooling mechanism according to an embodiment of the present invention.
3 is a sectional view, and FIG. 4 is a sectional view of a sealing cooling mechanism for a package according to another embodiment of the present invention. 11, 12... Board, 12, 22... Cap, 1
3, 23... Semiconductor device, 14... Heat conduction means,
24...Thermal conductive paste, 15...Water cooling jacket,
16, 26...I/O pins.
Claims (1)
該半導体デバイスと熱膨脹係数が等しいかあるい
はほゞ整合するセラミツク材料からなる基板と、
該基板の熱膨脹係数に等しいかあるいはほゞ整合
する熱膨脹係数及び該基板より高い熱伝導率を有
する高熱伝導性セラミツク材料からなり、前記基
板上面に半田づけされて前記半導体デバイスを覆
い封止するキヤツプと、前記半導体デバイスの発
熱を前記キヤツプに伝えるために該半導体デバイ
ス上面と前記キヤプ内面との間に設けられた熱伝
達手段と、前記キヤツプに集められた熱を取り除
くため前記キヤツプ外表面に取り付られた冷却手
段とから構成されることを特徴とするパツケージ
の封止冷却機構。 ２ 前記基板材料としてムライトセラミツクを用
い、前記キヤツプ材料として炭化シリコンを用い
たことを特徴とする特許請求の範囲第１記載のパ
ツケージ封止冷却機構。 ３ 前記基板材料としてアルミナセラミツクを用
い、前記キヤツプ材料として銅―炭素繊維複合材
料を用いたことを特徴とする特許請求の範囲１項
記載のパツケージの封止冷却機構。 ４ 前記キヤツプに取り付られる冷却手段および
前記熱伝導手段の部品の内、全てもしくは一部を
前記キヤツプと一体に形成したことを特徴とする
特許請求の範囲１項記載のパツケージの封止冷却
機構。[Scope of Claims] 1. A substrate made of a ceramic material on which a plurality of semiconductor devices are mounted and whose thermal expansion coefficient is equal to or substantially matched to that of the semiconductor devices;
a cap made of a highly thermally conductive ceramic material having a coefficient of thermal expansion equal to or substantially matching that of the substrate and a thermal conductivity higher than that of the substrate, and soldered to the upper surface of the substrate to cover and seal the semiconductor device; a heat transfer means provided between the top surface of the semiconductor device and the inner surface of the cap for transmitting heat generated by the semiconductor device to the cap; and a heat transfer means provided on the outer surface of the cap for removing heat collected in the cap. A sealed cooling mechanism for a package, comprising a cooling means attached thereto. 2. The package sealing cooling mechanism according to claim 1, wherein mullite ceramic is used as the substrate material, and silicon carbide is used as the cap material. 3. The package sealing cooling mechanism according to claim 1, wherein alumina ceramic is used as the substrate material, and a copper-carbon fiber composite material is used as the cap material. 4. A sealed cooling mechanism for a package according to claim 1, wherein all or a part of the cooling means and the heat conduction means attached to the cap are formed integrally with the cap. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24765383A JPS60143653A (en) | 1983-12-30 | 1983-12-30 | Sealing and cooling mechanism of package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24765383A JPS60143653A (en) | 1983-12-30 | 1983-12-30 | Sealing and cooling mechanism of package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60143653A JPS60143653A (en) | 1985-07-29 |
| JPS6412098B2 true JPS6412098B2 (en) | 1989-02-28 |
Family
ID=17166679
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24765383A Granted JPS60143653A (en) | 1983-12-30 | 1983-12-30 | Sealing and cooling mechanism of package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60143653A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4914551A (en) * | 1988-07-13 | 1990-04-03 | International Business Machines Corporation | Electronic package with heat spreader member |
| JPH0612795B2 (en) * | 1989-11-07 | 1994-02-16 | 株式会社日立製作所 | Multi-chip module cooling structure |
| JPH04192552A (en) * | 1990-11-27 | 1992-07-10 | Nec Corp | Package for semiconductor use |
| US5880524A (en) * | 1997-05-05 | 1999-03-09 | Intel Corporation | Heat pipe lid for electronic packages |
| JP2001053205A (en) * | 1999-08-05 | 2001-02-23 | Hitachi Ltd | Sealing and cooling device for multichip module |
| CN110010574B (en) * | 2018-12-29 | 2021-02-09 | 浙江臻镭科技股份有限公司 | Multilayer stacked longitudinally interconnected radio frequency structure and manufacturing method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58196041A (en) * | 1982-05-12 | 1983-11-15 | Hitachi Ltd | Thermal conduction connecting device |
-
1983
- 1983-12-30 JP JP24765383A patent/JPS60143653A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60143653A (en) | 1985-07-29 |
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