JPS6411013U - - Google Patents

Info

Publication number
JPS6411013U
JPS6411013U JP10394187U JP10394187U JPS6411013U JP S6411013 U JPS6411013 U JP S6411013U JP 10394187 U JP10394187 U JP 10394187U JP 10394187 U JP10394187 U JP 10394187U JP S6411013 U JPS6411013 U JP S6411013U
Authority
JP
Japan
Prior art keywords
ladder
hybrid circuit
shaped hybrid
stub
impedance matching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10394187U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10394187U priority Critical patent/JPS6411013U/ja
Publication of JPS6411013U publication Critical patent/JPS6411013U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例の構成を示すパター
ンの平面図。第2図は従来例の構成を示すパター
ンの平面図。 1および1′……はしご形ハイブリツド回路、
2および2′……RF入力端子、3および3′…
…ローカル信号入力端子、4および4′……IF
出力端子、5および5′……IFポート、6a,
6b,6a′および6b′……ダイオード、7お
よび7′……インピーダンスマツチング用スタブ
、8および8′……インダクタ。
FIG. 1 is a plan view of a pattern showing the configuration of an embodiment of the present invention. FIG. 2 is a plan view of a pattern showing the configuration of a conventional example. 1 and 1'...Ladder type hybrid circuit,
2 and 2'...RF input terminal, 3 and 3'...
...Local signal input terminal, 4 and 4'...IF
Output terminals, 5 and 5'...IF port, 6a,
6b, 6a' and 6b'...Diode, 7 and 7'...Stub for impedance matching, 8 and 8'...Inductor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] マイクロストリツプラインで構成されたはしご
形ハイブリツド回路を用いたマイクロ波平衡形ミ
クサーにおいて、インピーダンスマツチング用ス
タブをはしご形ハイブリツド回路の内側に設けた
ことを特徴とするマイクロ波平衡形ミクサー。
A microwave balanced mixer using a ladder-shaped hybrid circuit configured with microstrip lines, characterized in that a stub for impedance matching is provided inside the ladder-shaped hybrid circuit.
JP10394187U 1987-07-08 1987-07-08 Pending JPS6411013U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10394187U JPS6411013U (en) 1987-07-08 1987-07-08

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10394187U JPS6411013U (en) 1987-07-08 1987-07-08

Publications (1)

Publication Number Publication Date
JPS6411013U true JPS6411013U (en) 1989-01-20

Family

ID=31335219

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10394187U Pending JPS6411013U (en) 1987-07-08 1987-07-08

Country Status (1)

Country Link
JP (1) JPS6411013U (en)

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