JPS6410636A - Manufacture of hybrid integrated circuit - Google Patents
Manufacture of hybrid integrated circuitInfo
- Publication number
- JPS6410636A JPS6410636A JP62166326A JP16632687A JPS6410636A JP S6410636 A JPS6410636 A JP S6410636A JP 62166326 A JP62166326 A JP 62166326A JP 16632687 A JP16632687 A JP 16632687A JP S6410636 A JPS6410636 A JP S6410636A
- Authority
- JP
- Japan
- Prior art keywords
- silicon wafer
- electrode
- silicon
- collet
- quartz
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
Landscapes
- Wire Bonding (AREA)
Abstract
PURPOSE:To accurately pile up silicon chips by a method wherein an electrode formed on a first substrate is aligned with an electrode formed on a second substrate by using an infrared optical system. CONSTITUTION:A silicon wafer 3 where an electrode 10 coated with flux 1 for soldering use and containing a diced part 2 is placed on a quartz-sheet holder 4 of an infrared aligner. Then, a sliced chip 6 containing a solder bump 5 to be mounted on the silicon wafer 3 is attached to a collet (a vacuum-suction jig) 7 and is placed directly under a microscope 8. Then, while the microscope is moved upward and downward (for adjustment of a focal distance) and the quartz-sheet holder is shifted in an X-Y direction, an electrode pattern 9 of the upper-part silicon chip 6 is aligned with the electrode pattern 10 for solder bump connection use of the lower-part silicon wafer 3 while infrared rays 11 are being irradiated. when an alignment operation has been completed, the silicon chip 6 is pressed downward by using the collet 7 and is fixed temporarily via the flux 1 for soldering use. The above process is repeated.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62166326A JPS6410636A (en) | 1987-07-02 | 1987-07-02 | Manufacture of hybrid integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62166326A JPS6410636A (en) | 1987-07-02 | 1987-07-02 | Manufacture of hybrid integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6410636A true JPS6410636A (en) | 1989-01-13 |
Family
ID=15829284
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62166326A Pending JPS6410636A (en) | 1987-07-02 | 1987-07-02 | Manufacture of hybrid integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6410636A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0393244A (en) * | 1989-09-06 | 1991-04-18 | Shinkawa Ltd | Pattern detection of semiconductor parts and bonding |
CN101966635A (en) * | 2010-10-18 | 2011-02-09 | 卓盈微电子(昆山)有限公司 | Improved quartz table for use in chip welding |
-
1987
- 1987-07-02 JP JP62166326A patent/JPS6410636A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0393244A (en) * | 1989-09-06 | 1991-04-18 | Shinkawa Ltd | Pattern detection of semiconductor parts and bonding |
CN101966635A (en) * | 2010-10-18 | 2011-02-09 | 卓盈微电子(昆山)有限公司 | Improved quartz table for use in chip welding |
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