JPS641045A - Buffer memory circuit device - Google Patents
Buffer memory circuit deviceInfo
- Publication number
- JPS641045A JPS641045A JP63024926A JP2492688A JPS641045A JP S641045 A JPS641045 A JP S641045A JP 63024926 A JP63024926 A JP 63024926A JP 2492688 A JP2492688 A JP 2492688A JP S641045 A JPS641045 A JP S641045A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- request
- buffer memory
- memory
- mrd
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE: To delay the next request in case of a write interval to process the request after the delay time by coupling a buffer memory circuit to a request source and receiving the next address during block transfer and processing the next received request unless the buffer memory is in the write interval.
CONSTITUTION: A buffer memory circuit device 10 is connected between a request source 11 and a main storage 13, and a request signal RQ is continuously supplied to the device 10 from the request source 11. The device 10 generates a memory request signal NRQ and a memory address signal MAD in relation to the signal RQ and an address signal AD and sends them to the storage 12. The storage 12 supplies continuous memory reply data unit signal MRD and memory rely signal MRP to the device 10 in response to these signals NRQ and MAD respectively. The signal MRD executes block transfer, and blocks are continuously sent from the device 12 to the device 10, and execution is transferred from the first signal MRD to the last if there are no blocks in the device 10.
COPYRIGHT: (C)1989,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63024926A JPS641045A (en) | 1987-02-07 | 1988-02-06 | Buffer memory circuit device |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2557487 | 1987-02-07 | ||
JP62-25576 | 1987-02-07 | ||
JP62-25574 | 1987-02-07 | ||
JP63024926A JPS641045A (en) | 1987-02-07 | 1988-02-06 | Buffer memory circuit device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH011045A JPH011045A (en) | 1989-01-05 |
JPS641045A true JPS641045A (en) | 1989-01-05 |
Family
ID=26362508
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63024926A Pending JPS641045A (en) | 1987-02-07 | 1988-02-06 | Buffer memory circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS641045A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61228540A (en) * | 1985-04-01 | 1986-10-11 | Nec Corp | Cache memory control system |
-
1988
- 1988-02-06 JP JP63024926A patent/JPS641045A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61228540A (en) * | 1985-04-01 | 1986-10-11 | Nec Corp | Cache memory control system |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0059794A3 (en) | Data processing system | |
EP0307945A3 (en) | Memory control apparatus for use in a data processing system | |
EP0380093A3 (en) | Data transfer controller using dummy signals for continued operation under insignificant faulty conditions | |
DE3277424D1 (en) | Coupler for processors | |
JPS641045A (en) | Buffer memory circuit device | |
JPS6478362A (en) | One connection preparation of several data processors for central clock control multi-line system | |
JPS5793462A (en) | Disc cash system | |
JPS641046A (en) | Memory access control system | |
JPS6446145A (en) | Cache memory control system | |
JPS5724088A (en) | Buffer memory control system | |
JPS5644925A (en) | Control system of data processing system | |
JPS54140439A (en) | Composite computer device | |
JPS556614A (en) | Input-output data transfer control system | |
JPS57176442A (en) | Information processing system | |
JPS5597655A (en) | Memory access system | |
JPS6476337A (en) | Processing system for updating file | |
JPS559247A (en) | Input method of process data | |
JPS6486263A (en) | Data processor | |
JPS5478637A (en) | Information transfer control unit | |
ES8103407A1 (en) | Data processing system | |
JPS5694425A (en) | Receiving data transfer control system | |
JPS5668832A (en) | Data buffer control system | |
JPS6476132A (en) | Inter-storage unit page data transfer control system | |
JPS56111354A (en) | Loop-back control circuit | |
JPS5680724A (en) | Dma control system of data processing system |