JPS6396966A - Manufacture of thin film static induction type field-effect transistor - Google Patents
Manufacture of thin film static induction type field-effect transistorInfo
- Publication number
- JPS6396966A JPS6396966A JP24373286A JP24373286A JPS6396966A JP S6396966 A JPS6396966 A JP S6396966A JP 24373286 A JP24373286 A JP 24373286A JP 24373286 A JP24373286 A JP 24373286A JP S6396966 A JPS6396966 A JP S6396966A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode
- grid electrode
- type
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000006698 induction Effects 0.000 title claims abstract description 13
- 239000010409 thin film Substances 0.000 title claims abstract description 8
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 230000005669 field effect Effects 0.000 title claims description 10
- 230000003068 static effect Effects 0.000 title abstract description 6
- 239000010408 film Substances 0.000 claims abstract description 61
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 17
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 11
- 238000010030 laminating Methods 0.000 claims description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 abstract description 8
- 238000005530 etching Methods 0.000 abstract description 7
- 238000000059 patterning Methods 0.000 abstract description 4
- 229910052697 platinum Inorganic materials 0.000 abstract description 4
- 238000000151 deposition Methods 0.000 abstract 2
- 239000007789 gas Substances 0.000 description 18
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 229910000077 silane Inorganic materials 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- RFCAUADVODFSLZ-UHFFFAOYSA-N 1-Chloro-1,1,2,2,2-pentafluoroethane Chemical compound FC(F)(F)C(F)(F)Cl RFCAUADVODFSLZ-UHFFFAOYSA-N 0.000 description 4
- 235000019406 chloropentafluoroethane Nutrition 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- AJDIZQLSFPQPEY-UHFFFAOYSA-N 1,1,2-Trichlorotrifluoroethane Chemical compound FC(F)(Cl)C(F)(Cl)Cl AJDIZQLSFPQPEY-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical class O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910001120 nichrome Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 150000003839 salts Chemical class 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
Description
本発明は、高速駆動が可能な非晶質シリコン薄膜を用い
た静電誘導型電界効果トランジスタの製造方法に関する
。The present invention relates to a method for manufacturing a static induction field effect transistor using an amorphous silicon thin film that can be driven at high speed.
静電誘導型電界効果トランジスタのチャネル領域をシリ
コンを主成分とする非晶質半導体薄膜で構成したものは
、特公昭６０−２２４２８０号公報で公知である。その
代表例として、築出氏その他により第１１回国際非晶質
および液体半導体国際会議議事１ｔ（Ｐｒｏｃ、１１ｔ
ｈ Ｉｎｔｅｒｎ、 Ｃｏｎｆ、 ｏｎ Ａｍ
ｏｒｐｈｏｕｓ ＆Ｌｉｑｕｉｄ Ｓｅｍ１ｃｏａ
ｄｕｃｔｏｒｓ、Ｒｏｍｅ＋５ｅｐｔ ２ − ６
＋１９８５）に開示された第２図に示すものがある０
図において、絶縁基板１の上に金属電極２．アモルファ
ス・シリコン（ａ−５ｉ）のｎ型Ｎ３１．ノンドープ層
４、ｎ型層３２が積層され、ノンドープ層４中にグリン
トＮ極５が点在している。さらに、ｎ型Ｂ５３２の上に
金［ｔＦｉ ６が被着されている。このような静電誘導
型電界効果トランジスタの製造過程を第３図に示す、先
ず、図１ａ）に示すようにガラス基板１の上にニクロふ
Ｍ２を蒸着法により形成し、その上にシラン（ＳｉＨ４
）ガスにフォスフイン（ｐＨ３）を微量混合したガスを
反応ガスとして用いるプラズマＣＶＤ法によりｎ型ａ−
３＋層３１を、さらにシランガスを反応ガスとして用い
るプラズマＣＶＤ法によりノンドープａ −５ｒｉ４１
を形成する。 Ｆｒ１４１の厚さは２−程度である０次
に、図中）に示すようなフォトレジストパターン７をフ
ォトエツチングで形成し、この上に図＜ｃ＋のようにｐ
ｔからなる金属薄膜５０を５００〜２０００人の厚さに
蒸着する。この基板をフォトレジストのｆＪＩ＃液に浸
漬することにより、フォトレジスト７とその上の白金Ｗ
！Ｘ５０が除去されるリフトオフ法によって、図（ｄｌ
のように白金パターン５を形成する。さらに図（６１に
示すように、シランガスを用いるプラズマＣＶＤ法のよ
うに再びノンドープａ −５ｉ膜４２を約０．５ ｎの
膜厚に堆積し、さらにその上にシランガスにフォスフイ
ンガスを１ｉ混合した反応ガスを用いるプラズマＣＶＤ
法によりｎ型ａ−３ｉ膜３２を、つづいてＭ金属電極膜
６を形成する。
こうして形成した静Ｚ ７ａ導型トランジスタのＭ電極
６をアース電位とし、ニクロム電極２に３ｖを印加した
状態でゲート電圧をθ〜−４ｖの範囲で変えると、電流
値がｔｏ−” Ａから１０−” Ａ程度に低下すること
が見い出された。しかし、このようなｎ電誘導トランジ
スタでは、白金グリッド″ｒ！ｌ極５のパターンが背理
よく形成されず、突起がでることによりアース電位のへ
ｌ電極６との短絡が発生することがしばしばあり、正し
くトランジスタ動作するデバイスがなかなか得られない
という問題があった。A static induction field effect transistor in which the channel region is made of an amorphous semiconductor thin film containing silicon as a main component is known from Japanese Patent Publication No. 60-224280. As a representative example, Mr. Tsukuide et al. Proceedings of the 11th International Conference on Amorphous and Liquid Semiconductors
h Intern, Conf, on Am
orphous & Liquid Sem1coa
ductors, Rome+5ept 2-6
There is one shown in Figure 2 disclosed in +1985)0
In the figure, metal electrodes 2. Amorphous silicon (a-5i) n-type N31. A non-doped layer 4 and an n-type layer 32 are stacked, and glint N-poles 5 are scattered in the non-doped layer 4. Furthermore, gold [tFi 6 is deposited on top of the n-type B532. The manufacturing process of such an electrostatic induction field effect transistor is shown in FIG. 3. First, as shown in FIG. SiH4
n-type a-
3+ layer 31 is further non-doped a-5ri41 by a plasma CVD method using silane gas as a reaction gas.
form. The thickness of the Fr141 is approximately 2-0th order. Then, a photoresist pattern 7 as shown in the figure is formed by photoetching, and on top of this a photoresist pattern 7 as shown in the figure
A thin metal film 50 consisting of T is deposited to a thickness of 500 to 2000 mm. By immersing this substrate in the photoresist fJI# solution, the photoresist 7 and the platinum W on it are removed.
! Figure (dl
A platinum pattern 5 is formed as shown in FIG. Furthermore, as shown in Figure 61, a non-doped a-5i film 42 is deposited again to a thickness of about 0.5 nm using the plasma CVD method using silane gas, and on top of that, 1 i of phosphine gas is mixed with the silane gas. Plasma CVD using reactive gas
An n-type a-3i film 32 and then an M metal electrode film 6 are formed by the method. When the M electrode 6 of the static Z7a conductive transistor thus formed is set to ground potential and the gate voltage is varied in the range of θ to -4V with 3V applied to the nichrome electrode 2, the current value changes from to-''A to 10V. -” It was found that it decreased to about A. However, in such an n-type induction transistor, the pattern of the platinum grid "r!l" electrode 5 is not formed in a logical manner, and a short circuit with the ground potential electrode 6 often occurs due to protrusions. However, there was a problem in that it was difficult to obtain devices with proper transistor operation.
本発明は、第一？！極上に第一のｎ型ａ −５ｉ膜を被
着し、その上に第一のドープされないａ −５ｉ膜を４
ｆｌｉしたのち金属膜を被着し、その金属膜の表面にレ
ジストパターンを形成したのちエツチングしてグリッド
電極を形成し、さらにその上に第二のドープされないａ
−３ｉｌ１１．第二のｎ型ａ −３ｉｌｌｉおよび第二
電極膜を積層するもので、グリッド電極のパターンが精
度よく形成され、グリッド電極と第二１を極との短絡が
生じ、ないので上記の目的が達成される。Is this invention the first? ! A first n-type a-5i film is deposited on top, and a first undoped a-5i film is deposited on top of the first n-type a-5i film.
After fli, a metal film is deposited, a resist pattern is formed on the surface of the metal film, and then etched to form a grid electrode, and a second undoped a
-3il11. By laminating the second n-type a-3illi and the second electrode film, the pattern of the grid electrode is formed with high precision, and there is no short circuit between the grid electrode and the second electrode, so the above purpose is achieved. be done.
第１図（ａｌ〜（ｅｌは、本発明の第一の実施例の製造
工程を示し、第２．第３図と共通の部分は同一の符号を
付した０図１ａｌは第３図（ａｌと同一工程であり、ガ
ラス基板１の上に金属電極膜２．ｎ型ａ −Ｓｉ膜３１
、ノンドープａ−Ｓｌ膜４１を堆積したものである。
図（ｂｌはさらニソノ上ニ厚す５００〜２０００人（７
）Ｐｔｌ１５０をスパッタリングまたは電子ビーム蒸着
等により形成したものである０図（Ｃ１の工程において
、通常のフォトリソグラフィ法を用いてレジストパター
ン７を形成する０次いで、レジストパターン７をマスク
にしてｐｔをＱ、 ｌ ＴｏｒｒのＣＦ、ガス中でプラ
ズマエツチングした。高周波電力１００〜ｓｏｏ ｗを
加えることにより、数分でバターニングができた。
その後、レジスト７を酸素プラズマにより剥離すること
により、第１図（ｄｉに示すように金属パターン５が形
成された０次に、第１図（６１と同じく図（ｅｌの工程
において、ノンドープａ −５ｉｌｌ！４２を形成し、
さらにｎ型ａ−３ｉ）１１３２．金属電極６を順次堆積
した。この工程をとることにより、グリッド電極５とソ
ース電極６との短絡が減少し、特性良好な静電誘導型電
界効果トランジスタを得ることができた。
第一の実施例の変形として、工程（ｄｉにおけるｐｔの
エツチングを塩Ｍｌに対して硝酸３〜７を混合したもの
で行った。この場合、ｐｔのエツチングは数分で終了し
、良好なｐｔパターンを得ることができた。トランジス
タ特性もＣＦ４ガスでドライエツチングしたものと比較
して同程度のものが得られた。
第４図に本発明の第二の実施例による静電誘導型電界効
果トランジスタを示す、第２図と共通の部分は同一の符
号で示すが、金属電極５がｐ型膜−３ｉ膜８で囲まれて
いる。第５図＋８）〜（Ｃ）に第二の実施例の製造工程
を示す０図（ａｌは、ガラス基板ｌ上にＣｒ等から成る
金属電極膜２＋ｎ型ａ −３ｔ膜３１゜ノンドープミー
５ｉ膜４１を順次形成後、ｐ型膜 −３ｔ膜８１をシラ
ンガスに１％ジボランガスを混合したガスをグロー放電
分解することにより厚さ１００〜１０００人形成したこ
とを示す０次に、図伽）の工程において、金属グリッド
電極５を形成した。この電極は、Ｃｒｐ／ｌをスパッタ
リングで約１０００人形成後、フォトリソグラフィ法を
用いて図のようにパターン化した。Ｃｒのバターニング
は、０． Ｉ ＴｏｒｒのＣＣＩ。
＋ｏ！混合ガスにプラズマ電界を加えてエツチングする
ことにより行った０次に図（Ｃ１の工程において、ｐ型
膜 −５ｔ膜８２を１００〜１０００人の厚さに堆積形
成した０図（ｄｌの工程では、ｐ型膜 −３ｉ膜８２の
上にグリッド電極パターン５を覆う大きさのレジストパ
ターン７１を形成し、これを０．２ ＴｏｒｒでＳＦ、
とフロン１１３（ＣｔＣＩＦ、）を１：２に混合したガ
ス中に置き、数百Ｗの高周波電力を加え、ｐ型膜 −５
ｉ膜８１、８２のエツチングを行った。ノンドープａ
−５ｉ膜４１がエツチングされないように、エツチング
時間を制御することによって図＋ｄ＋のようにグリッド
電奢！！Ｉ５を包むｐ型膜−３１膜８のパターンを形成
した０次に＠離液によってレジスト７１をｍ離後、図（
ｓｌに示すようにノンドープミー５ｉ層４２を０．５
ｔｎａ ＋ｎｎ型膜−５ｉＪ！１３２を５００人、 Ｃ
ｒ電極６を１０００〜５０００人の厚さにそれぞれ堆積
形成した。
この結果、グリッド電極５とソース電極６との短絡がさ
らに低減し、良品率が第一の実施例の２倍程度に向上す
るばかりでな（、ｐ型膜−３ｉ膜８とａ−ＳｉＭ４との
間の接合により空乏層が広がりやすいので特性を向上し
た。またこの構造をとることにより、グリッド電極５に
ＰＬ、 Ｃｒのみならず、Ｎｉ、 Ｔｉ、 Ａｊその他
任意のものでパターニング性のいいものを用いることが
できるという利点が得られた。
第６図（ａ）〜（Ｃ１は、第５図に示した第二の実施例
の製造工程の変形例を示す、すなわち、第５図（ａ）。
ｔｂ＋の工程につづいて第６図（ａ）に示すように、金
属電極５をマスクとし、ＳＰｂとフロン１１５の混合ガ
スを用いて、ｐ型膜−Ｓｉ層８１をエツチングする。
次に、図ｆｂｌの工程においてシランガスとジボランガ
スの温きガスをプラズマ分解し、ｐ型膜−Ｓｉ層８２を
形成する。このｐ型膜−３ｉ１５８２上に、図（Ｃ）に
示すようにフォトレジストパターン７１を金属電極パタ
ーン５を覆う大きさで形成する。これをＳＦ４とフロン
１１３の混合ガスを用いてエツチングすることにより第
５図１ｄｌと同様な構造を得る。
第７図Ｇこ２三の実施例による静電誘導型電界効果トラ
ンジスタを示す。この場合は、ノンドープａ−３ＩＷ４
の中にｐ型膜 ５ｉＮ８３＋金属電極５゜ｐ型膜−Ｓ
ｉｉ８４から成るグリッド電極を形成したものである。
第８図（ａ）〜（Ｃ１はその製造工程を示す。
図１ａｌの工程では、ガラス基板１の上に金属電極２゜
ｎ型膜−５ｉ膜３１．ノンドープａ−３ｔ膜４１．厚さ
１００〜１０００人のｐ型膜−３ｉ８１．厚さ約１００
０人のＣｒ１１２５０゜厚さ１００〜１０００人のｐ型
膜 −５ｉ８２を順次積層堆積する０図中）の工程では
、フォトリソグラフィ法を用いてレジストパターン７１
を形成後これをマスクとしてｐ型ＦＪ８１をＳＰｈとフ
ロン１１５の混合ガスで、Ｃｒ膜５０をＣＣ１＃＋Ｏｌ
ガスで、再びｐ型層８２をＳＦ。
とフロン１１５の混合ガスでプラズマエツチングした０
次の図（ｅ）の工程では、レジスト膜７１を！Ａ離後、
約０６５−厚のノンドープａ Ｓ＋１１４２． ｎ
型膜 −３ｉ膜３２．金属電極６を順次堆積した。この
結果、素子特性としては第二の実施例に近いものが得ら
れた。しかしこの実施例では、同一パターンのｐ型Ｊｉ
８３．８４でＣｒ’１Ｌｊ５をはさんだ構造とし、この
パターンは同一マスクで形成できるので、工程が簡略化
できるという利点がある。
なお、上記の第二、第三の実施例のｐ型膜の代わりに絶
縁膜を用いてグリッド電極をＭＩＳ構造にすることも有
効である。Figure 1 (al to (el) indicates the manufacturing process of the first embodiment of the present invention, and parts common to Figures 2 and 3 are given the same reference numerals. Figure 1al is Figure 3 (al This is the same process as above, and a metal electrode film 2 and an n-type a-Si film 31 are formed on the glass substrate 1.
, a non-doped a-Sl film 41 is deposited. Figure (bl is 500 to 2000 people (7)
) Ptl150 is formed by sputtering or electron beam evaporation, etc. (In the step C1, a resist pattern 7 is formed using an ordinary photolithography method.) Next, using the resist pattern 7 as a mask, pt is , l Torr of CF gas. By applying high frequency power of 100 to sow, patterning was completed in a few minutes. Thereafter, the resist 7 was peeled off using oxygen plasma to form the pattern shown in Fig. 1 ( After the metal pattern 5 is formed as shown in di, a non-doped a-5ill!42 is formed in the step of FIG.
Furthermore, n-type a-3i) 1132. Metal electrodes 6 were sequentially deposited. By taking this step, short circuits between the grid electrode 5 and the source electrode 6 were reduced, and an electrostatic induction field effect transistor with good characteristics could be obtained. As a modification of the first example, the etching of PT in the step (di) was carried out using a mixture of 3 to 7 nitric acids to salt Ml. In this case, the etching of PT was completed in a few minutes, and a good PT A pattern was obtained.The transistor characteristics were also comparable to those obtained by dry etching with CF4 gas.Figure 4 shows the electrostatic induction field effect according to the second embodiment of the present invention. The same parts as in Fig. 2, which show the transistor, are indicated by the same reference numerals, but the metal electrode 5 is surrounded by the p-type film -3i film 8. Fig. 5+8) to (C) show the second implementation. Figure 0 showing the manufacturing process of an example (al is a metal electrode film 2 made of Cr etc., an n-type a-3t film 31, and a non-doped me-5i film 41 are sequentially formed on a glass substrate l, and then a p-type film -3t film 81 is formed on the glass substrate l. The metal grid electrode 5 was formed in the process shown in Figure 3, which shows that it was formed to a thickness of 100 to 1000 by glow discharge decomposition of a mixture of silane gas and 1% diborane gas. This electrode was formed by sputtering Crp/l to form about 1000 layers, and then patterned using photolithography as shown in the figure. Cr buttering is 0. CCI of I Torr. +o! A 0-order diagram (in the step C1, a p-type film 82 was deposited to a thickness of 100 to 1000 layers (in the dl step) was obtained by etching by applying a plasma electric field to a mixed gas. , a resist pattern 71 having a size that covers the grid electrode pattern 5 is formed on the p-type film -3i film 82, and is subjected to SF at 0.2 Torr.
The p-type film -5
The i-films 81 and 82 were etched. non-dope a
By controlling the etching time so that the -5i film 41 is not etched, the grid voltage is reduced as shown in Figure +d+. ! After forming the pattern of p-type film-31 film 8 surrounding I5 and separating the resist 71 by m by syneresis, the pattern shown in FIG.
As shown in sl, the non-doped Mi5i layer 42 is 0.5
tna +nn type membrane-5iJ! 132 to 500 people, C
The r electrodes 6 were each deposited to a thickness of 1000 to 5000 layers. As a result, the short-circuit between the grid electrode 5 and the source electrode 6 is further reduced, and the yield rate is improved to about twice that of the first embodiment. The characteristics were improved because the depletion layer spreads easily due to the junction between the two electrodes.By adopting this structure, the grid electrode 5 can be made of not only PL and Cr, but also Ni, Ti, Aj, and other arbitrary materials with good patterning properties. 6(a) to (C1) show a modification of the manufacturing process of the second embodiment shown in FIG. ).Following the tb+ process, as shown in FIG. 6(a), the p-type film-Si layer 81 is etched using a mixed gas of SPb and Freon 115, using the metal electrode 5 as a mask.Next, In the process shown in Figure fbl, warm gases of silane gas and diborane gas are plasma decomposed to form a p-type film-Si layer 82.A photoresist pattern 71 is formed on this p-type film-3i1582 as shown in Figure (C). is formed in a size that covers the metal electrode pattern 5. By etching this using a mixed gas of SF4 and Freon 113, a structure similar to that shown in FIG. 5 1dl is obtained. In this case, a non-doped a-3IW4
p-type film inside 5iN83 + metal electrode 5゜p-type film-S
A grid electrode made of ii84 is formed. 8(a) to 8(C1) show the manufacturing process. In the process of FIG. ~1000 p-type membrane-3i81.Thickness approx. 100
In the step (in Figure 0) of sequentially stacking the p-type film -5i82 of 11250° thickness and 100 to 1000 layers of Cr11250°, a resist pattern 71 is formed using photolithography.
After forming the Cr film 50 using this as a mask, the p-type FJ81 is coated with a mixed gas of SPh and Freon 115.
SF the p-type layer 82 again with gas. Plasma etched with a mixed gas of CFC and Freon 115
In the next step shown in Figure (e), the resist film 71 is removed! After leaving A,
Approximately 065-thick non-doped a S+1142. n
Type film -3i film 32. Metal electrodes 6 were sequentially deposited. As a result, device characteristics close to those of the second example were obtained. However, in this embodiment, p-type Ji with the same pattern
The structure is such that Cr'1Lj5 is sandwiched between 83 and 84 layers, and this pattern can be formed using the same mask, which has the advantage of simplifying the process. Note that it is also effective to use an insulating film instead of the p-type film in the second and third embodiments described above to form the grid electrode into an MIS structure.
本発明によれば、グリッド電極を蒸着等により全面に形
成した金属膜からレジストパターンを用いたエツチング
によりバターニングすることにより、リフトオフ法によ
る場合に生ずるグリッド電極とソース電極との短絡が抑
えられ、薄膜静電誘導型電界効果トランジスタの製造歩
留り向上にすぐれた効果が得られた。According to the present invention, by patterning the grid electrode from a metal film formed over the entire surface by vapor deposition or the like by etching using a resist pattern, short circuits between the grid electrode and the source electrode that occur when using the lift-off method can be suppressed. An excellent effect was obtained in improving the manufacturing yield of thin film electrostatic induction field effect transistors.
第１図は本発明の第一の実施例の製造工程を順次示す断
面図、第２図は第１図の工程で製造されるトランジスタ
の断面図、第３図は第２図のトランジスタの従来の製造
工程を順次示す断面図、第４図は本発明の第二の実施例
によって製造されるトランジスタの断面図、第５図は第
二の実施例の工程を順次示す断面図、第６図は第５図の
工程の変形例を順次示す断面図、第７図は本発明の第三
の実施例によって製造されるトランジスタの断面図、第
８図は第三の実施例の工程の要部を順次示す断面図であ
る。
１：絶縁基板、２．６：金属電掻膜、３１．３２：ｎ型
ａ−３ｉ膜、４．４１．４２：ノンドープａ −３１膜
、５ニゲリツド電極、？、７１： レジスト、８．８１
゜８２：ｐ型ａ −５ｉ膜。
士 ” 、ｉ） Ｌ／ ｊｊ
第１図
第４図
―
ψ1 is a cross-sectional view sequentially showing the manufacturing process of the first embodiment of the present invention, FIG. 2 is a cross-sectional view of a transistor manufactured by the process of FIG. 1, and FIG. 3 is a conventional transistor of the transistor shown in FIG. 2. FIG. 4 is a cross-sectional view of a transistor manufactured according to the second embodiment of the present invention, FIG. 5 is a cross-sectional view sequentially showing the steps of the second embodiment, and FIG. are cross-sectional views sequentially showing variations of the process shown in FIG. 5, FIG. 7 is a cross-sectional view of a transistor manufactured according to the third embodiment of the present invention, and FIG. 8 is a main part of the process of the third embodiment. It is sectional drawing which shows sequentially. 1: Insulating substrate, 2.6: Metal electroplated film, 31.32: N-type a-3i film, 4.41.42: Non-doped a-31 film, 5 nigerid electrode, ? , 71: Resist, 8.81
°82: p-type a-5i film. ``, i) L/ jj Figure 1 Figure 4 - ψ
Claims (1)
、その上に第一のドープされない非晶質シリコン膜を積
層したのち金属膜を被着し、該金属膜の表面にレジスト
パターンを形成したのちエッチングして金属グリッド電
極を形成し、さらにその上に第二のドープされない非晶
質シリコン膜、第二のｎ型非晶質シリコン膜および第二
電極膜を積層することを特徴とする薄膜静電誘導電界効
果トランジスタの製造方法。 ２）特許請求の範囲第１項記載のトランジスタにおいて
、金属グリッド電極とドープされない非晶質シリコン膜
との間にｐ型非晶質シリコン膜を介在させることを特徴
とする薄膜静電誘導電界効果トランジスタの製造方法。 ３）特許請求の範囲第１項記載のトランジスタにおいて
、金属グリッド電極とドープされない非晶質シリコン膜
との間に絶縁膜を介在させることを特徴とする薄膜静電
誘導型電界効果トランジスタの製造方法。[Claims] 1) A first n-type amorphous silicon film is deposited on the first electrode, a first undoped amorphous silicon film is laminated thereon, and then a metal film is deposited. A resist pattern is formed on the surface of the metal film and then etched to form a metal grid electrode, and a second undoped amorphous silicon film, a second n-type amorphous silicon film and a second n-type amorphous silicon film are formed on the resist pattern. A method for manufacturing a thin film electrostatic induction field effect transistor, comprising laminating a second electrode film. 2) In the transistor according to claim 1, a thin film electrostatic induction field effect characterized in that a p-type amorphous silicon film is interposed between the metal grid electrode and the undoped amorphous silicon film. Method of manufacturing transistors. 3) A method for manufacturing a thin film electrostatic induction field effect transistor according to claim 1, characterized in that an insulating film is interposed between the metal grid electrode and the undoped amorphous silicon film. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24373286A JPS6396966A (en) | 1986-10-14 | 1986-10-14 | Manufacture of thin film static induction type field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24373286A JPS6396966A (en) | 1986-10-14 | 1986-10-14 | Manufacture of thin film static induction type field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6396966A true JPS6396966A (en) | 1988-04-27 |
Family
ID=17108165
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24373286A Pending JPS6396966A (en) | 1986-10-14 | 1986-10-14 | Manufacture of thin film static induction type field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6396966A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001135828A (en) * | 1999-03-12 | 2001-05-18 | Sumitomo Chem Co Ltd | Iii-v compound semiconductor and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60224280A (en) * | 1984-04-20 | 1985-11-08 | Nippon Sheet Glass Co Ltd | Electrostatic induction type field effect transistor |
| JPS61199668A (en) * | 1985-03-01 | 1986-09-04 | Toshiba Corp | Manufacture of semiconductor device |
| JPS62213171A (en) * | 1986-03-13 | 1987-09-19 | Fujitsu Ltd | Manufacture of electrostatic induction thin-film transistor |
-
1986
- 1986-10-14 JP JP24373286A patent/JPS6396966A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60224280A (en) * | 1984-04-20 | 1985-11-08 | Nippon Sheet Glass Co Ltd | Electrostatic induction type field effect transistor |
| JPS61199668A (en) * | 1985-03-01 | 1986-09-04 | Toshiba Corp | Manufacture of semiconductor device |
| JPS62213171A (en) * | 1986-03-13 | 1987-09-19 | Fujitsu Ltd | Manufacture of electrostatic induction thin-film transistor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001135828A (en) * | 1999-03-12 | 2001-05-18 | Sumitomo Chem Co Ltd | Iii-v compound semiconductor and manufacturing method thereof |
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