WO1989009494A1 - Gate dielectric for a thin film field effect transistor - Google Patents

Gate dielectric for a thin film field effect transistor Download PDF

Info

Publication number
WO1989009494A1
WO1989009494A1 PCT/US1989/000971 US8900971W WO8909494A1 WO 1989009494 A1 WO1989009494 A1 WO 1989009494A1 US 8900971 W US8900971 W US 8900971W WO 8909494 A1 WO8909494 A1 WO 8909494A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
dielectric
thin film
gate dielectric
gate
Prior art date
Application number
PCT/US1989/000971
Other languages
French (fr)
Inventor
Anthony W. Catalano
Ralph C. Kerns
Original Assignee
Solarex Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Solarex Corporation filed Critical Solarex Corporation
Publication of WO1989009494A1 publication Critical patent/WO1989009494A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT

Definitions

  • the present invention relates to a thin film transis ⁇ tor device, and more particularly, to an improved gate dielec ⁇ tric for a thin film transistor.
  • Thin film transistors generally comprise source and drain electrodes interconnected by a central layer of semiconductor material having a thickness less than l ⁇ .
  • the device operates by creating a conducting channel beneath a source electrode and a drain electrode.
  • the current flow between the electrodes is controlled by the application of a voltage to a gate which is adjacent to, but insulated from, a portion of the semiconductor material.
  • a positive bias is applied to the gate electrode, negative charges accumulate in the otherwise low conductivity layer of semiconductor material.
  • the conductivity of the semiconductor material layer is increased, and a source-drain current can be made to flow under the appropriate bias.
  • the gate dielectric mate ⁇ rial is patterned to form a central portion over a planar por ⁇ tion of the gate region and to cover any exposed gate edges.
  • atomic level defects in the dielectric material or at the dielectric/ semiconductor interface can occur causing charges to become trapped in the dielectric layer. Any charge trapped in the dielectric layer or at the dielectric/semiconductor inter ⁇ face can degrade performance of the thin film transistor and give rise to hysteresis in the performance and other time depen ⁇ dent phenomenon that limit the usefulness of the device in
  • charge leakage lowers the on/off source-drain current ratio of the device.
  • pinholes can occur which can .cause short circuits to occur if a pinhole is under the source or drain.
  • a gate dielectric mate ⁇ rial for a thin film transistor which effectively prohibits charges from becoming trapped in the dielectric layer or at the dielectric/semiconductor interface and which is free of pin ⁇ holes. It would further be desirable to have a dielectric mate ⁇ rial with a high dielectric constant for good electrical isola ⁇ tion characteristics thereby permitting high electric fields to be applied to the semiconductor thus improving performance and permitting high voltages to be switched. And it would also be desirable to have a gate dielectric material comprised of a thin film material thereby maintaining the thin aspect of the overall thin film field effect transistor.
  • the invention comprises a dielectric for a gate of a thin film field effect transistor, comprising a first layer of an insu ⁇ lating thin film crystalline or amorphous material formed on the gate and a second layer of silicon nitride formed on the first layer.
  • Fig. 1 is a cross-sectional diagram illustrating a gate dielectric for a thin film field effect transistor in accordance with an embodiment of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENT
  • the transistor is formed on a substrate 10 of a suit ⁇ able material, such as glass.
  • a gate electrode 12 is deposited on the substrate 10.
  • the gate electrode 12 is formed of a suit ⁇ able metal, such as nichrome or molybdenum.
  • a first layer of gate dielectric material 14 is comprised of insulating thin film material is deposited on the gate electrode 12 and the substrate 10 by a process of atmo ⁇ spheric chemical vapor deposition using a 5 to 6 percent (atom ⁇ ic) solution of SiH in N2 and O2.
  • the first layer of gate dielectric material 14 may be comprised of silicon dioxide (Si ⁇ 2).
  • the first thin film layer is deposited at about 540°C to form a layer of gate dielectric material 14 approximately 800 to 2,500 angstroms thick when measured from the gate electrode 12 to the top of the first layer of gate dielectric material 14.
  • the first layer of gate dielectric material 14 may also be comprised of tantalum pentoxide (Ta2 ⁇ s) or silicon dioxide or a compound of silicon and nitrogen having a chemical formula SiN x , where x is a number in the range of 0.1 to 1.33 and is prefereably equal to 1.33.
  • the device can be further improved by exposing the first layer of gate dielectric material 14 to a plasma etch using a solution of CF4-O2 or NF3 in order to remove any contam ⁇ ination due to atmospheric exposure, oxidation, or moisture.
  • second layer of gate dielectric material 16 is deposited on the first layer of gate dielectric material 14.
  • the second layer of- gate dielectric material 16 is silicon nitride and is approximately 1,000 angstroms thick when measured from the gate electrode 12 to the top of the gate dielectric material 16.
  • the first layer of gate dielectric material 14 of in ⁇ sulating thin film material is chosen to provide a high dielec ⁇ tric constant.
  • silicon dioxide has a dielectric constant equal to 4 and tantalum pentoxide has a dielectric material constant equal to 25.
  • the second layer of dielectric 16 should also have a high dielectric constant, but it is pri ⁇ marily chosen in order to eliminate pinholes which could occur in the first layer 14 and to provide a clean interface to the subsequent semiconductor layer.
  • Silicon nitride for example, appears to cover up any pinholes that may occur in the first layer of dielectric material 14.
  • any charge leakage which could cause charges to become trapped in the first layer 14 thereby lowering the on/off source-drain current ratio is pre ⁇ vented.
  • the device of the present invention achieves an on/off source-drain current ratio equal to about 10' and a breakdown voltage which is greater than 100 volts, as opposed to a break ⁇ down voltage in prior thin film transistors of from 20 to 40 volts.
  • a semiconductor layer 30 is deposited over the second gate dielectric layer 16, the first gate dielectric layer 14, the gate electrode 12, and over the substrate 10 preferably by using a glow discharge plasma of silane method.
  • This method of deposition which is well known to those in the art as glow dis ⁇ charge, is described in U.S. Patent No. 4,064,521, which is hereby incorporated herein by reference.
  • Semiconductor layer 30 is preferably hydrogenated amorphous silicon (a-Si:H) which pro ⁇ vides desirable properties for a thin film field effect transis ⁇ tor such as would be known to one of ordinary skill in the field of thin film transistor fabrication.
  • n+ conductivity type semiconductor material 32 is deposited over the semiconductor layer 30, which can also be comprised of hydrogenated amorphous silicon. N-type conduction occurs when a material has been doped to create excess charge carriers which thereby increase the on-current flow.
  • a source electrode 18 and a drain electrode 20 are deposited over the layer 32.
  • the source electrode 18 and the drain electrode 20 are acid etched and then patterned.
  • Source electrode 18 and drain electrode 20 are spaced apart and layer 32 is subjected to a plasma etch leaving a portion of the semiconductor layer 30 exposed which partially overlays the sec ⁇ ond layer of gate dielectric material 16, the first layer of gate dielectric material 14, and the gate electrode 12.
  • the source electrode 18 and drain electrode 20 are preferably alumi ⁇ num, however, magnesium, molybdenum, nichrome, or other suitable conductive metals, mixtures of these metals, or alloys of these metals may be used.
  • the double-layer gate dielectric of the present inven ⁇ tion prevents pinholes from occurring in the gate dielectric material and prevents charge leakage which could give rise to undesirable time dependent phenomenon and which could lower the on/off source-drain current ratio. Moreover, both layers of dielectric material are chosen to obtain high dielectric con ⁇ stants, thereby achieving a high breakdown voltage.

Abstract

A thin film field effect transistor utilizes a double-layer of dielectric material with a first layer (14) of an insulating crystalline or amorphous material and a second layer (16) of silicon nitride. The first layer has a high dielectric constant and the second layer eliminates pinholes which could occur in the first layer.

Description

GATE DIELECTRIC FOR A THIN
FILM FIELD EFFECT TRANSISTOR
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a thin film transis¬ tor device, and more particularly, to an improved gate dielec¬ tric for a thin film transistor. Description of the Related Art
In recent years, there has been growing interest in thin film transistors and devices incorporating such thin film transistors, such as various integrated circuits and flat panel displays such as those which employ liquid crystals. Thin film transistors generally comprise source and drain electrodes interconnected by a central layer of semiconductor material having a thickness less than lμ .
In a typical thin film field effect transistor, the device operates by creating a conducting channel beneath a source electrode and a drain electrode. The current flow between the electrodes is controlled by the application of a voltage to a gate which is adjacent to, but insulated from, a portion of the semiconductor material. When a positive bias is applied to the gate electrode, negative charges accumulate in the otherwise low conductivity layer of semiconductor material. Thus, the conductivity of the semiconductor material layer is increased, and a source-drain current can be made to flow under the appropriate bias.
A gate dielectric material used to provide electrical isolation while permitting an electric field to be applied to the semiconductor and to reduce shorts and capacitance between the gate and the source or the drain. The gate dielectric mate¬ rial is patterned to form a central portion over a planar por¬ tion of the gate region and to cover any exposed gate edges. Sometimes, when the dielectric material is of inferior quality, atomic level defects in the dielectric material or at the dielectric/ semiconductor interface can occur causing charges to become trapped in the dielectric layer. Any charge trapped in the dielectric layer or at the dielectric/semiconductor inter¬ face can degrade performance of the thin film transistor and give rise to hysteresis in the performance and other time depen¬ dent phenomenon that limit the usefulness of the device in
SUBSTITUTESHEET -2-
practical applications. ;:Additionally, charge leakage lowers the on/off source-drain current ratio of the device. Furthermore, when the dielectric matrial is of inferior quality, pinholes can occur which can .cause short circuits to occur if a pinhole is under the source or drain.
It would be desirable to have a gate dielectric mate¬ rial for a thin film transistor which effectively prohibits charges from becoming trapped in the dielectric layer or at the dielectric/semiconductor interface and which is free of pin¬ holes. It would further be desirable to have a dielectric mate¬ rial with a high dielectric constant for good electrical isola¬ tion characteristics thereby permitting high electric fields to be applied to the semiconductor thus improving performance and permitting high voltages to be switched. And it would also be desirable to have a gate dielectric material comprised of a thin film material thereby maintaining the thin aspect of the overall thin film field effect transistor.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a gate dielectric material with a high dielectric con¬ stant and which prevents charges from becoming trapped in the dielectric layer.
It is a further object of the invention to provide a gate dielectric layer which is free of pinholes.
It is an additional object of the invention to provide a gate dielectric layer which is made of a thin film material.
Additional objects and advantages of this invention will be set forth in part in the description which follows and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instru¬ mentalities and combinations particularly pointed out in the appended clams.
To achieve the objects and in accordance with the pur¬ pose of the invention, as embodied and broadly described herein, the invention comprises a dielectric for a gate of a thin film field effect transistor, comprising a first layer of an insu¬ lating thin film crystalline or amorphous material formed on the gate and a second layer of silicon nitride formed on the first layer.
The accompanying drawing, which is incorporated in and constitutes a part of this specification, illustrates an embodi¬ ment of the invention and, together with the description, serves to explain the principles of the invention.
BRIEF DESCRIPTION OF THE DRAWING
Fig. 1 is a cross-sectional diagram illustrating a gate dielectric for a thin film field effect transistor in accordance with an embodiment of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENT
Reference will now be made in detail to the present preferred embodiment of the invention, an example of which is illustrated in the drawing.
The transistor is formed on a substrate 10 of a suit¬ able material, such as glass. A gate electrode 12 is deposited on the substrate 10. The gate electrode 12 is formed of a suit¬ able metal, such as nichrome or molybdenum.
Then, a first layer of gate dielectric material 14 is comprised of insulating thin film material is deposited on the gate electrode 12 and the substrate 10 by a process of atmo¬ spheric chemical vapor deposition using a 5 to 6 percent (atom¬ ic) solution of SiH in N2 and O2. The first layer of gate dielectric material 14 may be comprised of silicon dioxide (Siθ2). Preferably, the first thin film layer is deposited at about 540°C to form a layer of gate dielectric material 14 approximately 800 to 2,500 angstroms thick when measured from the gate electrode 12 to the top of the first layer of gate dielectric material 14. The first layer of gate dielectric material 14 may also be comprised of tantalum pentoxide (Ta2θs) or silicon dioxide or a compound of silicon and nitrogen having a chemical formula SiNx, where x is a number in the range of 0.1 to 1.33 and is prefereably equal to 1.33.
The device can be further improved by exposing the first layer of gate dielectric material 14 to a plasma etch using a solution of CF4-O2 or NF3 in order to remove any contam¬ ination due to atmospheric exposure, oxidation, or moisture. -4-
-* >r--Ne" t. -a."second layer of gate dielectric material 16 is deposited on the first layer of gate dielectric material 14. Preferably",- the second layer of- gate dielectric material 16 is silicon nitride and is approximately 1,000 angstroms thick when measured from the gate electrode 12 to the top of the gate dielectric material 16.
The first layer of gate dielectric material 14 of in¬ sulating thin film material is chosen to provide a high dielec¬ tric constant. For example, silicon dioxide has a dielectric constant equal to 4 and tantalum pentoxide has a dielectric material constant equal to 25. The second layer of dielectric 16 should also have a high dielectric constant, but it is pri¬ marily chosen in order to eliminate pinholes which could occur in the first layer 14 and to provide a clean interface to the subsequent semiconductor layer. Silicon nitride, for example, appears to cover up any pinholes that may occur in the first layer of dielectric material 14. Also, any charge leakage which could cause charges to become trapped in the first layer 14 thereby lowering the on/off source-drain current ratio is pre¬ vented. The device of the present invention achieves an on/off source-drain current ratio equal to about 10' and a breakdown voltage which is greater than 100 volts, as opposed to a break¬ down voltage in prior thin film transistors of from 20 to 40 volts.
After the gate dielectric layers 14 and 16 are deposited, a semiconductor layer 30 is deposited over the second gate dielectric layer 16, the first gate dielectric layer 14, the gate electrode 12, and over the substrate 10 preferably by using a glow discharge plasma of silane method. This method of deposition, which is well known to those in the art as glow dis¬ charge, is described in U.S. Patent No. 4,064,521, which is hereby incorporated herein by reference. Semiconductor layer 30 is preferably hydrogenated amorphous silicon (a-Si:H) which pro¬ vides desirable properties for a thin film field effect transis¬ tor such as would be known to one of ordinary skill in the field of thin film transistor fabrication. However, other suitable semiconductor materials may be used, such as crystalline or polycrystalline silicon and gallium arsenide as would be known to one skilled in the art of thin film transistor design. Next, a layer of n+ conductivity type semiconductor material 32 is deposited over the semiconductor layer 30, which can also be comprised of hydrogenated amorphous silicon. N-type conduction occurs when a material has been doped to create excess charge carriers which thereby increase the on-current flow.
Lastly, a source electrode 18 and a drain electrode 20 are deposited over the layer 32. The source electrode 18 and the drain electrode 20 are acid etched and then patterned. Source electrode 18 and drain electrode 20 are spaced apart and layer 32 is subjected to a plasma etch leaving a portion of the semiconductor layer 30 exposed which partially overlays the sec¬ ond layer of gate dielectric material 16, the first layer of gate dielectric material 14, and the gate electrode 12. The source electrode 18 and drain electrode 20 are preferably alumi¬ num, however, magnesium, molybdenum, nichrome, or other suitable conductive metals, mixtures of these metals, or alloys of these metals may be used.
The double-layer gate dielectric of the present inven¬ tion prevents pinholes from occurring in the gate dielectric material and prevents charge leakage which could give rise to undesirable time dependent phenomenon and which could lower the on/off source-drain current ratio. Moreover, both layers of dielectric material are chosen to obtain high dielectric con¬ stants, thereby achieving a high breakdown voltage.
It will be apparent to those skilled in the art that various modifications and variations can be made in the appara¬ tus of the present invention without departing from the scope or spirit of the invention. Thus, it is intended that the present invention cover the modif cations and variations of this inven¬ tion provided they come within the scope of the appended claims and their equivalents.

Claims

WHAT IS CLAIMED IS:
1. A dielectric for a gate of a thin film field effect transistor, comprising: a first layer of insulating thin film crystalline or amorphous material formed on said gate; and a second layer of silicon nitride formed on said first layer.
2. The dielectric of claim 1 wherein said first layer is comprised of silicon dioxide (Siθ2).
3. The dielectric of claim 1 wherein said first layer is comprised of tantalum pentoxide (Ta2θs).
4. The dielectric of claim 1 wherein said first layer is 800 to 2,500 angstroms thick and wherein said second layer is 1,000 angstroms thick.
5. The dielectric of claim 1 wherein said first layer is fabricated by depositing a layer of silicon dioxide using chemical vapor deposition and a 5 to 6 percent (atomic) solution of SiH in N2 and O2.
6. The dielectric of claim 5 wherein said chemical vapor is deposited at about 540°C.
7. The dielectric of claim 1 wherein said first layer is copmrised of silicon dioxide and a compound of silicon and nitrogen having the chemical formula SiNx, where x is a num¬ ber in the range of 0.1 to 1.33.
8. The dielectric of claim 1 wherein the first layer has a dielectric constant approximately equal to 4.0.
9. The dielectric of claim 3 wherein the first layer has a dielectric constant approximately equal to 25.
PCT/US1989/000971 1988-03-31 1989-03-14 Gate dielectric for a thin film field effect transistor WO1989009494A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17626488A 1988-03-31 1988-03-31
US176,264 1988-03-31

Publications (1)

Publication Number Publication Date
WO1989009494A1 true WO1989009494A1 (en) 1989-10-05

Family

ID=22643652

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1989/000971 WO1989009494A1 (en) 1988-03-31 1989-03-14 Gate dielectric for a thin film field effect transistor

Country Status (2)

Country Link
EP (1) EP0408653A4 (en)
WO (1) WO1989009494A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5013692A (en) * 1988-12-08 1991-05-07 Sharp Kabushiki Kaisha Process for preparing a silicon nitride insulating film for semiconductor memory device
US5580815A (en) * 1993-08-12 1996-12-03 Motorola Inc. Process for forming field isolation and a structure over a semiconductor substrate
US5918147A (en) * 1995-03-29 1999-06-29 Motorola, Inc. Process for forming a semiconductor device with an antireflective layer

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3922774A (en) * 1972-05-01 1975-12-02 Communications Satellite Corp Tantalum pentoxide anti-reflective coating
GB2153589A (en) * 1984-01-30 1985-08-21 Sharp Kk Thin film transistor
US4543133A (en) * 1983-04-30 1985-09-24 Fujitsu Limited Process for producing single crystalline semiconductor island on insulator
US4639087A (en) * 1984-08-08 1987-01-27 Energy Conversion Devices, Inc. Displays having pixels with two portions and capacitors
US4698787A (en) * 1984-11-21 1987-10-06 Exel Microelectronics, Inc. Single transistor electrically programmable memory device and method
JPH0686863A (en) * 1992-09-07 1994-03-29 Ace Denken:Kk Pachinko game machine

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4242156A (en) * 1979-10-15 1980-12-30 Rockwell International Corporation Method of fabricating an SOS island edge passivation structure
JPS58147069A (en) * 1982-02-25 1983-09-01 Sharp Corp Thin film transistor
US4876582A (en) * 1983-05-02 1989-10-24 Ncr Corporation Crystallized silicon-on-insulator nonvolatile memory device
JPS60109285A (en) * 1983-11-17 1985-06-14 Seiko Instr & Electronics Ltd Thin film transistor
GB2169746B (en) * 1984-11-13 1988-09-14 Sharp Kk Thin film transistor

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3922774A (en) * 1972-05-01 1975-12-02 Communications Satellite Corp Tantalum pentoxide anti-reflective coating
US4543133A (en) * 1983-04-30 1985-09-24 Fujitsu Limited Process for producing single crystalline semiconductor island on insulator
GB2153589A (en) * 1984-01-30 1985-08-21 Sharp Kk Thin film transistor
US4639087A (en) * 1984-08-08 1987-01-27 Energy Conversion Devices, Inc. Displays having pixels with two portions and capacitors
US4698787A (en) * 1984-11-21 1987-10-06 Exel Microelectronics, Inc. Single transistor electrically programmable memory device and method
JPH0686863A (en) * 1992-09-07 1994-03-29 Ace Denken:Kk Pachinko game machine

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
M. MATSUMURA, "Amorphous Silicon Transistors and Integrated Circuits", Japanese Journal of Applied Physics, Volume 22 (1983) Supplement 22-1, pages 487 to 491, see especially figure 1. *
S. M. SZE, Semiconductor Devices Physics & Technology, John Wiley & Sons (1981) page 344, pages 357, 360, 362. *
See also references of EP0408653A4 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5013692A (en) * 1988-12-08 1991-05-07 Sharp Kabushiki Kaisha Process for preparing a silicon nitride insulating film for semiconductor memory device
US5580815A (en) * 1993-08-12 1996-12-03 Motorola Inc. Process for forming field isolation and a structure over a semiconductor substrate
US5707889A (en) * 1993-08-12 1998-01-13 Motorola Inc. Process for forming field isolation
US5918147A (en) * 1995-03-29 1999-06-29 Motorola, Inc. Process for forming a semiconductor device with an antireflective layer

Also Published As

Publication number Publication date
EP0408653A1 (en) 1991-01-23
EP0408653A4 (en) 1991-10-16

Similar Documents

Publication Publication Date Title
US3475234A (en) Method for making mis structures
US4668968A (en) Integrated circuit compatible thin film field effect transistor and method of making same
US6097096A (en) Metal attachment method and structure for attaching substrates at low temperatures
US4673957A (en) Integrated circuit compatible thin film field effect transistor and method of making same
US3514676A (en) Insulated gate complementary field effect transistors gate structure
US9646963B1 (en) Integrated circuits with capacitors and methods for producing the same
US5550397A (en) Metal oxide semiconductor transistors having a polysilicon gate electrode with nonuniform doping in source-drain direction
US5130264A (en) Method of making a thin film transistor
KR20040021758A (en) Method for fabricating of a poly-Si TFT
US4722913A (en) Doped semiconductor vias to contacts
KR100272260B1 (en) Thin film transistor using diamond like carbon and manufacturing method thereof
JPH03116875A (en) Thin film field effect transistor and method of manufacturing the same
US4327477A (en) Electron beam annealing of metal step coverage
JPH0828502B2 (en) Bidirectional power vertical MOS device and method of manufacturing the same
US6117751A (en) Method for manufacturing a mis structure on silicon carbide (SiC)
KR19980065168A (en) Thin film transistor using fluorine-containing oxide film as gate insulating film and manufacturing method thereof
WO1989009494A1 (en) Gate dielectric for a thin film field effect transistor
US5397721A (en) Method for fabricating vertical thin film transistor
KR100675317B1 (en) Thin Film Transistor and Fabricating Method Thereof
US6323114B1 (en) Stacked/composite gate dielectric which incorporates nitrogen at an interface
JPS60177676A (en) Thin film transistor device and manufacture thereof
JPS59163871A (en) Double gate type thin-film transistor
JPS5914672A (en) Manufacture of thin film transistor
JPS62219574A (en) Semiconductor device
JP2668459B2 (en) Insulation film manufacturing method

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP KR

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE FR GB IT LU NL SE

WWE Wipo information: entry into national phase

Ref document number: 1989904998

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 1989904998

Country of ref document: EP

WWR Wipo information: refused in national office

Ref document number: 1989904998

Country of ref document: EP

WWW Wipo information: withdrawn in national office

Ref document number: 1989904998

Country of ref document: EP