JPS6396949A - Mos constant-voltage circuit - Google Patents
Mos constant-voltage circuitInfo
- Publication number
- JPS6396949A JPS6396949A JP61242483A JP24248386A JPS6396949A JP S6396949 A JPS6396949 A JP S6396949A JP 61242483 A JP61242483 A JP 61242483A JP 24248386 A JP24248386 A JP 24248386A JP S6396949 A JPS6396949 A JP S6396949A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- fet
- vth
- vout
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000015654 memory Effects 0.000 description 2
- 230000001276 controlling effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はＭＯＳトランジスタで構成した定電圧発生回路
に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a constant voltage generating circuit composed of MOS transistors.
従来の技術
ダイナミックメモリー等のダウンコンバータ等に用いら
れる定電圧発生回路では、ゲートとドレインを共通にし
たＭＯＳトランジスタ数ケと負荷抵抗を直列に接続して
目的の電圧を発生する方法がよく用られる。ゲートとド
レインを共通にしたＭＯＳ）う／ジスタの動作は飽和領
域であるから、特性は
β
ｉ＝＝ −（ｖ −Ｖ ）２ ・・・・・・・
・・・・・（１） ＧＳ Ｔ
で表わされ、この式から出力電圧は
となる。したがってβが充分大きなトランジスタで構成
すれば、
ｖ０＝ ＶＴ ・・・・・−・・・・・・
（３）となり、ｎヶ直列にした場合は
Ｖｏ ＝ｎＶ７ ・・・・・・・・・・・・
（４となってＶＴに依存した定電圧を発生することが可
能である。Conventional technology In constant voltage generation circuits used in down converters such as dynamic memories, a method is often used in which several MOS transistors with a common gate and drain are connected in series with a load resistor to generate the desired voltage. . Since the operation of a MOS transistor with a common gate and drain is in the saturation region, the characteristics are β i== −(v −V )2 .
...(1) It is expressed as GST, and from this formula, the output voltage becomes. Therefore, if the transistor is constructed with a sufficiently large β, v0=VT ・・・・・・−・・・・・・
(3), and when n units are connected in series, Vo = nV7 ・・・・・・・・・・・・
(It is possible to generate a constant voltage depending on VT.
但し、ｖＴはＭＯＳトランジスタのしきい値電圧、■は
ドレイン・ノース間の電流、ｖＧｓ はゲート・ソース
間電圧である。Here, vT is the threshold voltage of the MOS transistor, ■ is the current between the drain and north, and vGs is the voltage between the gate and source.
発明が解決しようとする問題点
一方、ＭＯＳトランジスタのしきい値電圧ｖＴは製造の
際、ロフト間、ウェーハ間、チップ間で大巾にばらつく
ことがあり、ｎ段構成するとｎ倍にばらつきも大きくな
り、定電圧回路の出力のばらつきが数１０ｍＶ〜１００
ｍＶ にもなってしまうという問題点がある。Problems to be Solved by the Invention On the other hand, during manufacturing, the threshold voltage vT of a MOS transistor can vary widely between lofts, between wafers, and between chips, and when configured with n stages, the variation is n times larger. Therefore, the variation in the output of the constant voltage circuit is several tens of mV to 100 mV.
There is a problem in that it becomes even mV.
本発明はかかる点に鑑みてなされたもので、簡単な構成
で、ＭＯＳトランジスタのしきい値電圧依存性の少ない
ＭＯ８形定電圧回路を提供するものである。The present invention has been made in view of these points, and it is an object of the present invention to provide an MO8 type voltage regulating circuit that has a simple configuration and is less dependent on the threshold voltage of a MOS transistor.
問題点を解決するための手段
本発明は上記問題を解決するため、定電圧を発生するた
めのＮ段直列のゲート・ドレインを共通にしたｎチャネ
ルＭＯ３トランジスタの負荷としてｐチャネルＭＯＳト
ランジスタを設け、さらにその直列回路と並列にＮ＋１
段もしくはＮ ＋ ｎ段のゲート・ドレインを共通にし
た前記ｎチャネルトランジスタと同一のトランジスタお
よび負荷抵抗を直列接続し、その出力を前記ｐチャネル
トランジスタのゲートに印加して、出力段のｎチャネル
トランジスタのしきい値電圧のばらつきによる、出力電
圧のばらつきを補正するものである。Means for Solving the Problems In order to solve the above problems, the present invention provides a p-channel MOS transistor as a load for N-channel MO3 transistors connected in series with a common gate and drain for generating a constant voltage. Furthermore, N+1 in parallel with that series circuit
A transistor that is the same as the n-channel transistor having a common gate and drain in the N+n stage and a load resistor is connected in series, and its output is applied to the gate of the p-channel transistor, so that the n-channel transistor in the output stage is This is to correct variations in output voltage due to variations in threshold voltage.
作 用
本発明は上記した構成により、出力段のｎチャンネルト
ランジスタと同一特性の電圧検出用のトランジスタ回路
の電圧によって出力段の負荷であるｐチャネルトランジ
スタのゲート電圧を制御し、出力段の電流値を制御する
ことによって出力電圧からしきい値電圧依存性を補正す
ることができる。According to the above-described configuration, the present invention controls the gate voltage of the p-channel transistor, which is the load of the output stage, by the voltage of the voltage detection transistor circuit having the same characteristics as the n-channel transistor of the output stage, and adjusts the current value of the output stage. By controlling the output voltage, it is possible to correct the threshold voltage dependence from the output voltage.
実施例
以下に本発明の一実施例について図面とともに説明する
。図は本発明の定電圧回路の一実施例を示す回路図であ
る。図において、１は負荷抵抗、２．３，４．５はｎチ
ャネルＭＯＳトランジスタ、６はｐチャネルＭＯＳトラ
ンジスタ、７，８．９は２〜６と同様の特性を有するｎ
チャネルＭＯＳトランジスタである。この回路において
定電圧出力Ｖｏｕｔはｎチャネルトランジスタ７．８．
９のしきい値電圧がｖＴｎ とすると（４）式からおよ
そ３ｖＴｎ となる。したがって、このように直列に設
けたＭＯＳ トランジスタの段数によってＶｏｕｔを適
宜選択することができる。一方トランジスタ２のドレイ
ンには同様にほぼ４ｖＴｎ の電圧が出る。今、この回
路を同一チップ内に集積し、各ｎチャネルトランジスタ
のしきい値電圧ｖＴｎが同一であるとすれば、ｖＴｎが
高い時はｐチャネルトランジスタのゲート・ソース間電
圧が低く、そのためにトランジスタ６．７，８．９を流
れる電流が下がりＶｏｕｔが若干低くなる。ｖＴｎが低
い時はこの逆でＶｏｕｔは１〜６の補正回路が無い時に
比べて若干高くなる。つまり、本回路によれば、ｎチャ
ネルＭＯＳトランジスタのしきい値電圧ｖＴｎの高低に
かかわらず一定の出力電圧Ｖｏｕｔを保つことができる
。EXAMPLE An example of the present invention will be described below with reference to the drawings. The figure is a circuit diagram showing an embodiment of the constant voltage circuit of the present invention. In the figure, 1 is a load resistance, 2.3 and 4.5 are n-channel MOS transistors, 6 is a p-channel MOS transistor, and 7 and 8.9 are n-channel MOS transistors having the same characteristics as 2 to 6.
This is a channel MOS transistor. In this circuit, the constant voltage output Vout is the n-channel transistor 7.8.
If the threshold voltage of 9 is vTn, it becomes approximately 3vTn from equation (4). Therefore, Vout can be appropriately selected depending on the number of stages of MOS transistors arranged in series in this manner. On the other hand, a voltage of approximately 4vTn similarly appears at the drain of transistor 2. Now, if this circuit is integrated on the same chip and the threshold voltage vTn of each n-channel transistor is the same, when vTn is high, the gate-source voltage of the p-channel transistor is low, and therefore the transistor The current flowing through 6.7 and 8.9 decreases, and Vout becomes slightly lower. When vTn is low, the opposite is true, and Vout becomes slightly higher than when there are no correction circuits 1 to 6. In other words, according to this circuit, a constant output voltage Vout can be maintained regardless of the level of the threshold voltage vTn of the n-channel MOS transistor.
なお本実施例では出力段のｎチャネルＭＯＳトランジス
タを３段構成にし、しきい値検出段を４段構成にしたが
、トランジスタの数は任意に設定することができる。ま
たｐチャネルとｎチャネルトランジスタを入れ換えて構
成することも可能である。In this embodiment, the n-channel MOS transistors in the output stage are configured in three stages, and the threshold value detection stage is configured in four stages, but the number of transistors can be set arbitrarily. It is also possible to configure the device by replacing the p-channel and n-channel transistors.
発明の効果
以上述べてきたように、本発明によれば、きわめて簡単
な回路で、しきい値電圧依存性の少ない、ＭＯ３定電圧
回路を構成することができ、ダイナミックメモリー等の
ＬＳＩのダウンコンバータ等にきわめて有用である。Effects of the Invention As described above, according to the present invention, it is possible to configure an MO3 constant voltage circuit with a very simple circuit and less dependence on threshold voltage, and it can be used as a down converter for LSI such as dynamic memory. It is extremely useful for
図は本発明の一実施例におけるＭＯ３定電圧回路を示す
回路図である。
２．３，４．ｅｓ、７，８．９・・・・・・ｎチャネル
ＭＯＳトランジスタ、６・・・・・・ｐチャネルＭＯＳ
トランジスタ。The figure is a circuit diagram showing an MO3 constant voltage circuit in one embodiment of the present invention. 2.3,4. es, 7, 8.9...n channel MOS transistor, 6...p channel MOS
transistor.
Claims (1)
直列に接続した第１導電形のＭＯＳトランジスタと、前
記ＭＯＳトランジスタと直列に設けた第２導電形のＭＯ
Ｓトランジスタと、前記第１導電形のＭＯＳトランジス
タと同一の特性を有するゲートとドレインを共通にした
ＭＯＳトランジスタ列と、前記ＭＯＳトランジスタ列と
直列に設け、かつその接続点を前記第２導電形のＭＯＳ
トランジスタのゲートに接続する抵抗とを有してなるＭ
ＯＳ定電圧回路。One or more MOS transistors of a first conductivity type connected in series, each having a common gate and drain, and an MOS transistor of a second conductivity type provided in series with the MOS transistor.
an S transistor, a MOS transistor array having a common gate and drain having the same characteristics as the MOS transistor of the first conductivity type, and a MOS transistor array provided in series with the MOS transistor array, and a connecting point thereof is of the second conductivity type. M.O.S.
and a resistor connected to the gate of the transistor.
OS constant voltage circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61242483A JP2763531B2 (en) | 1986-10-13 | 1986-10-13 | MOS constant voltage circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61242483A JP2763531B2 (en) | 1986-10-13 | 1986-10-13 | MOS constant voltage circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6396949A true JPS6396949A (en) | 1988-04-27 |
| JP2763531B2 JP2763531B2 (en) | 1998-06-11 |
Family
ID=17089758
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61242483A Expired - Lifetime JP2763531B2 (en) | 1986-10-13 | 1986-10-13 | MOS constant voltage circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2763531B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103235631B (en) * | 2013-04-15 | 2015-07-08 | 无锡普雅半导体有限公司 | Voltage stabilizer circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62188255A (en) * | 1986-02-13 | 1987-08-17 | Toshiba Corp | Reference voltage generating circuit |
-
1986
- 1986-10-13 JP JP61242483A patent/JP2763531B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62188255A (en) * | 1986-02-13 | 1987-08-17 | Toshiba Corp | Reference voltage generating circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2763531B2 (en) | 1998-06-11 |
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