GB2265478A - Reference voltage generating circuit - Google Patents
Reference voltage generating circuit Download PDFInfo
- Publication number
- GB2265478A GB2265478A GB9209196A GB9209196A GB2265478A GB 2265478 A GB2265478 A GB 2265478A GB 9209196 A GB9209196 A GB 9209196A GB 9209196 A GB9209196 A GB 9209196A GB 2265478 A GB2265478 A GB 2265478A
- Authority
- GB
- United Kingdom
- Prior art keywords
- reference voltage
- whose
- voltage generating
- generating circuit
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 8
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
- G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
- G05F3/247—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage producing a voltage or current as a predetermined function of the supply voltage
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
- G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
- G05F3/245—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage producing a voltage or current as a predetermined function of the temperature
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Electromagnetism (AREA)
- Nonlinear Science (AREA)
- Automation & Control Theory (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Control Of Electrical Variables (AREA)
- Dram (AREA)
Description
12654-78 c.-- f 1 RE-FERENCE VOLTAGE GENERATING CIRCUIT The present
inventio n relates to a semiconductor device, and more particularly to a reference voltage generating circuit of a semiconductor device.
Reference voltage generating circuits are widely employed in digital/analog semiconductor devices, and a reference voltage generating circuit which is independent of variations in temperature and process becomes gradually necessary in MOS ICs. Therefore, a constant-voltage circuit which utilizes a bipolar transistor or a circuit which utilizes the threshold voltage difference of an enhancementtype MOS transistor or depletion MOS transistor, are designed. These conventional circuits can decrease the fluctuation of a reference voltage caused by the changes in temperature and process, but require additional processing. Moreover, the power dissipation in such a reference voltage generating circuit becomes greatly increased.
FIG. 1 of the accompanying drawings illustrates one example of a reference voltage generating circuit by a conventional technique. In FIG. 1, a resistor R connected between a power source Vcc and a reference voltage Vref is connected to a diode composed of a plurality of PMOS transistors between reference voltage Vref and ground Vss. Thus, since reference voltage Vref is in proportion to the threshold voltage Vt of a MOS transistor, reference voltage Vref fluctuates in accordance with the variation of threshold voltage of the MOS transistor due to the changes 2 in temperature and process.
FIG. 2 of the accompanying drawings is another example of a reference voltage generating circuit by a conventional technique. In FIG. 2, the circuit includes a resistor R connected between a power source Vcc and a reference voltage Vref, a MOS diode composed of a PMOS transistor having a source electrode connected to reference voltage Vref a gate electrode connected to its drain, and an NMOS transistor having a drain electrode connected to the drain electrode of the MOS diode and a gate electrode connected to the reference voltage V,, and a source electrode connected to the ground V,,. Therefore, the circuit outputs reference voltage Vref using the feedback loop by the NMOS transistor, wherein reference voltage Vref is represented by the sum of threshold voltage Vt of the PMOS transistor and the voltage drop across the NMOS transistor. If the temperature rises and then reference voltage Vref drops, the resistance of the NMOS transistor is increased relative to the drop, thereby raising reference voltage Vref. However, the value of reference voltage Vref is sensitively varied in accordance with the fluctuation of the power source voltage.
Accordingly, it is an object of the present invention to provide a reference voltage generating circuit of a semiconductor device, which is insusceptible to the changes in temperature and process.
It is another object of the present invention to provide a reference voltage generating circuit of a 3 semiconductor, which is insusceptible to the fluctuation in a power source voltage.
According to the present invention, there is provided a reference voltage generating circuit comprising:
means for generating a reference current; reference voltage generating means for outputting a reference voltage which is the product of the reference current and the resistance of resistor means by connecting the resistor means between the output terminal of the reference voltage generating means and ground, the resistor means being formed by serially connecting a MOS diode and a MOS transistor controlled by the reference voltage; and a current mirror circuit for inputting the current proportional to the reference current generated from the reference current generating means to the reference voltage generating means.
The reference voltage generating circuit of the present invention makes the reference voltage fluctuation insusceptible to the temperature and process variations.
Embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which:
FIG. 1 shows one example of a reference voltage generating circuit of a conventional semiconductor device; FIG. 2 shows another example of a reference voltage generating circuit of a conventional semiconductor device; FIG. 3 i! a circuit diagram of a reference voltage 4 generating circuit of a semiconductor device according to an embodiment of the present invention; and FIG. 4 is a graph representing the variation of reference current relative to a power source of the reference voltage generating circuit of Fig. 3.
The reference voltage generating circuit shown in Fig. 3 includes:
a reference current generating circuit 10 for generating reference current insusceptible to changes in temperature and process, which is formed of a PMOS transistor MP4 having its source electrode connected to power source voltage Vcc and a gate electrode connected to ground, an NMOS transistor MN3 having its drain electrode connected to the drain electrode of PMOS transistor MP4, and its source electrode connected to ground, an NMOS transistor MN2 having its gate electrode connected to the drain electrode of NMOS transistor MN3, and its source electrode connected to the gate electrode of NMOS transistor MN3, a resistor R, connected to the source electrode of NMOS transistor MN2, and an NMOS transistor MN4 having its drain electrode connected to resistor R,, and its source and gate electrodes commonly connected to ground; a current mirror 20 for mirroring the reference current, which is composed of a PMOS transistor MP1 having source electrode connected to a power source voltage, and gate and drain electrodes connected to the drain electrode of NMOS transistor MN2, and a PMOS transistor MP2 having its source electrode cpnnected to the power source voltage and a gate electrode connected to the gate electrode of PMOs transistor MP1; and a reference voltage generating circuit 30 formed by a PMOS transistor MP3 which has its source electrode connected to the drain electrode of PMOS transistor MP2, a substrate and a reference voltage output node, and commonly connected gate and drain electrodes, and an NMOS transistor MN1 which has its drain electrode connected to the drain electrode of PMOS transistor MP3, its gate electrode connected to the output node, and its source electrode connected to ground.
In the circuit shown in FIG. 3, reference current Iref can be represented as below:
Iref = VtMN3-VtMN4 R, where "VOON311 and "VUAN411 designate the threshold voltages of NMOS transistors MN3 and MN4, respectively.
In the above equation, reference current Iref is in proportion to the threshold voltage difference of NMOS transistors MN3 and MN4. Accordingly, Iref is insusceptible to the changes in temperature and process and independent of the power source voltage.
When reference current Iref flows through current mirror 20, reference voltage Vref is determined by reference current Iref independent of the power source voltage. Also, reference voltage Vref is determined by the sum of threshold voltage of PMOS tr4nsistor MP3 and NMOS transistor MN1.
6 FIG. 4 represents the reference current in accordance with the power source voltage of the reference current generating circuit, wherein it can be noted that current linearly increases up to 2 volts, but a constant current is generated thereafter.
In addition, the fluctuation of the reference voltage according to the temperature of the reference voltage generating circuit this embodiment according to the present invention is as follows:
temperature conventional art present invention (OC) (V) (V) -5 1.4725 1.3965 +25 1.4006 1.3972 +50 1.3396 1.3968 +100 1.2198 1.3905 1 1 As a result, the reference voltage generating circuit according to the present invention is insusceptible to the changes in temperature and process, and is independent of the fluctuation of the power source voltage. Further, a special mask or additional process is not required.
X 7
Claims (1)
- CLAIMS:1.A reference voltage generating circuit comprising: means for generating a reference current; reference voltage generating means for outputting a reference voltage which is the product of said reference current and the resistance of resistor means by connecting said resistor means between the output terminal of said reference voltage generating means and ground, said resistor means comprising a MOS diode and a MOS transistor connected in series controlled by said reference voltage; and a current mirror circuit for inputting current proportional to said reference current generated from said reference current generating means to said reference voltage generating means.2. A reference voltage generating circuit as claimed in claim 1, wherein said current mirror circuit allows a smaller amount of current than said reference current of said reference current generating circuit to flow in said reference voltage generating circuit according to the sizes of transistors forming said current mirror circuit.3. A reference voltage generating circuit as claimed in claim 1 or 2, wherein said MOS diode is a f irst PMOS transistor whose gate and drain electrodes are connected to each other, and whose source and substrate are commonly connected to said;eference voltage.8 4. A reference voltage generating circuit as claimed in claim 3, wherein said MOS transistor is a f irst NMOS transistor whose gate electrode is connected to said reference voltage, whose drain electrode is connected to said drain electrode of said f irst PMOS transistor, and whose source electrode is connected to ground.5. A reference voltage generating circuit as claimed claim 3 or 4, wherein said current mirror circuit comprises: a second PMOS transistor whose source electrode is connected to power source voltage, and whose drain electrode is commonly connected to its gate electrode; and a third PMOS transistor whose source electrode is connected to said power source voltage, whose gate electrode is connected to the gate electrode of said second PMOS transistor, and whose drain electrode is connected to the source electrode of said first PMOS transistor.6. A reference voltage generating circuit as claimed in claim 5, wherein said reference current generating circuit comprises: a f ourth PMOS transistor whose source electrode is connected to said power source voltage, and whose gate electrode is connected to ground; a second NMOS transistor whose drain electrode is connected to the drain electrode of said fourth PMOS transistor, and whose source electrode is connected to ground; 1 9 a third NMOS transistor whose drain electrode is connected to the drain electrode of said second PMOS transistor of said current mirror circuit, whose gate electrode is connected to the drain electrode of said second NMOS transistor, and whose source electrode is connected to the gate electrode of said second NMOS transistor7 a resistor connected to the source electrode of said third NMOS transistor; and a fourth NMOS transistor whose drain is connected to said resistor, and whose source and gate electrodes are commonly connected to ground.7. A reference voltage generating circuit comprising:reference voltage generating means for receiving a constant reference current and outputting a reference voltage which is the product of said reference current and the resistance of resistor means in which said resistor means is connected between the output terminal of said reference voltage generating means and ground, said resistor means comprising a MOS diode and a MOS transistor connected in series controlled by said reference voltage.1 8. A reference voltage generating circuit as claimed in claim 7, wherein said MOS diode is a PMOS transistor whose gate and drain electrodes are connected to each other, and whose source and substrate are commonly connected to said reference voltage.9. A reference voltage generating circuit as claimed in claim 7 or 8, wherein said MOS transistor is an NMOS transistor whose gate electrode is connected to said reference voltage, whose drain electrode is connected to the drain electrode of said PMOS transistor, and whose source electrode is connected to ground.10. A reference voltage generating circuit substantially as hereinbefore described with reference to FIG. 3 with or without reference to FIG. 4 ofthe accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920004474A KR950010284B1 (en) | 1992-03-18 | 1992-03-18 | Reference voltage generating circuit |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9209196D0 GB9209196D0 (en) | 1992-06-17 |
| GB2265478A true GB2265478A (en) | 1993-09-29 |
| GB2265478B GB2265478B (en) | 1996-01-03 |
Family
ID=19330566
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9209196A Expired - Fee Related GB2265478B (en) | 1992-03-18 | 1992-04-29 | Reference voltage generating circuit |
Country Status (7)
| Country | Link |
|---|---|
| JP (1) | JPH0643953A (en) |
| KR (1) | KR950010284B1 (en) |
| DE (1) | DE4214106A1 (en) |
| FR (1) | FR2688904B1 (en) |
| GB (1) | GB2265478B (en) |
| IT (1) | IT1254948B (en) |
| TW (1) | TW250603B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0713164A1 (en) * | 1994-11-15 | 1996-05-22 | STMicroelectronics Limited | A reference circuit |
| EP0733959A1 (en) * | 1995-03-24 | 1996-09-25 | Co.Ri.M.Me. Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno | Circuit for generating a reference voltage and detecting an undervoltage of a supply voltage and corresponding method |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100496792B1 (en) * | 1997-09-04 | 2005-09-08 | 삼성전자주식회사 | A reference voltage generating circuit |
| US6242972B1 (en) * | 1999-10-27 | 2001-06-05 | Silicon Storage Technology, Inc. | Clamp circuit using PMOS-transistors with a weak temperature dependency |
| KR101133758B1 (en) * | 2005-01-19 | 2012-04-09 | 삼성전자주식회사 | Sensor and thin film transistor array panel including sensor |
| JP5482126B2 (en) * | 2009-11-13 | 2014-04-23 | ミツミ電機株式会社 | Reference voltage generating circuit and receiving circuit |
| CN107015594A (en) * | 2017-05-30 | 2017-08-04 | 长沙方星腾电子科技有限公司 | A kind of bias current generating circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0112443A1 (en) * | 1982-10-29 | 1984-07-04 | International Business Machines Corporation | Reference voltage generating circuit |
| GB2238890A (en) * | 1989-10-24 | 1991-06-12 | Samsung Electronics Co Ltd | Circuit for stabilizing a reference voltage |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56121114A (en) * | 1980-02-28 | 1981-09-22 | Seiko Instr & Electronics Ltd | Constant-current circuit |
| US4464588A (en) * | 1982-04-01 | 1984-08-07 | National Semiconductor Corporation | Temperature stable CMOS voltage reference |
| US4847518A (en) * | 1987-11-13 | 1989-07-11 | Harris Semiconductor Patents, Inc. | CMOS voltage divider circuits |
| GB2214333B (en) * | 1988-01-13 | 1992-01-29 | Motorola Inc | Voltage sources |
| JP2674669B2 (en) * | 1989-08-23 | 1997-11-12 | 株式会社東芝 | Semiconductor integrated circuit |
-
1992
- 1992-03-18 KR KR1019920004474A patent/KR950010284B1/en not_active IP Right Cessation
- 1992-04-10 TW TW081102803A patent/TW250603B/zh active
- 1992-04-29 DE DE4214106A patent/DE4214106A1/en not_active Withdrawn
- 1992-04-29 FR FR9205286A patent/FR2688904B1/en not_active Expired - Fee Related
- 1992-04-29 GB GB9209196A patent/GB2265478B/en not_active Expired - Fee Related
- 1992-04-29 IT ITMI921017A patent/IT1254948B/en active IP Right Grant
- 1992-05-15 JP JP4123538A patent/JPH0643953A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0112443A1 (en) * | 1982-10-29 | 1984-07-04 | International Business Machines Corporation | Reference voltage generating circuit |
| GB2238890A (en) * | 1989-10-24 | 1991-06-12 | Samsung Electronics Co Ltd | Circuit for stabilizing a reference voltage |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0713164A1 (en) * | 1994-11-15 | 1996-05-22 | STMicroelectronics Limited | A reference circuit |
| US5654918A (en) * | 1994-11-15 | 1997-08-05 | Sgs-Thomson Microelectronics Limited | Reference circuit for supplying a reference level for sensing in a memory |
| EP0733959A1 (en) * | 1995-03-24 | 1996-09-25 | Co.Ri.M.Me. Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno | Circuit for generating a reference voltage and detecting an undervoltage of a supply voltage and corresponding method |
| US5747978A (en) * | 1995-03-24 | 1998-05-05 | Sgs-Thomson Microelectronics S.R.L. | Circuit for generating a reference voltage and detecting an under voltage of a supply and corresponding method |
Also Published As
| Publication number | Publication date |
|---|---|
| IT1254948B (en) | 1995-10-11 |
| GB2265478B (en) | 1996-01-03 |
| JPH0643953A (en) | 1994-02-18 |
| FR2688904B1 (en) | 1994-06-03 |
| ITMI921017A0 (en) | 1992-04-29 |
| ITMI921017A1 (en) | 1993-10-29 |
| DE4214106A1 (en) | 1993-09-23 |
| KR950010284B1 (en) | 1995-09-12 |
| GB9209196D0 (en) | 1992-06-17 |
| TW250603B (en) | 1995-07-01 |
| FR2688904A1 (en) | 1993-09-24 |
| KR930020658A (en) | 1993-10-20 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20000429 |