KR940005510B1 - Reference current generating circuit - Google Patents

Reference current generating circuit Download PDF

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KR940005510B1
KR940005510B1 KR1019920004658A KR920004658A KR940005510B1 KR 940005510 B1 KR940005510 B1 KR 940005510B1 KR 1019920004658 A KR1019920004658 A KR 1019920004658A KR 920004658 A KR920004658 A KR 920004658A KR 940005510 B1 KR940005510 B1 KR 940005510B1
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voltage
reference current
electrode connected
source electrode
transistor
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KR1019920004658A
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Korean (ko)
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KR930020847A (en
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이재형
이동재
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삼성전자 주식회사
김광호
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Priority to KR1019920004658A priority Critical patent/KR940005510B1/en
Priority to FR9205216A priority patent/FR2688903B1/en
Priority to CN92103104A priority patent/CN1065532A/en
Priority to ITMI921016A priority patent/IT1254947B/en
Priority to DE4214403A priority patent/DE4214403A1/en
Priority to GB9209400A priority patent/GB2265479A/en
Priority to JP4123528A priority patent/JPH0675648A/en
Publication of KR930020847A publication Critical patent/KR930020847A/en
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Publication of KR940005510B1 publication Critical patent/KR940005510B1/en

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
    • G05F3/245—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage producing a voltage or current as a predetermined function of the temperature
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
    • G05F3/247—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage producing a voltage or current as a predetermined function of the supply voltage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Automation & Control Theory (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Control Of Electrical Variables (AREA)
  • Dram (AREA)
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Abstract

The circuit is for the generation of stable reference current which is insensitive to the variation of ambient temperature and the change of manufacturing process. The curcuit includes a PMOS transistor (MP1) of which drain and gate are connected to the power source and ground respectively, a PMOS transistor (MP2) of which drain is connected to the power source and gate and source are shorted in common, an NMOS (MN2) transistor of which gate and drain are connected to the sources of MP1 and MP2 respectively, an NMOS (NM1) transistor of which drain and gate are connected to the gate and source of MN2.

Description

기준전류 발생회로Reference current generating circuit

제1도는 종래 기술에 따른 반도체 장치의 기준 전류 발생회로를 나타내는 것이다.1 shows a reference current generating circuit of a semiconductor device according to the prior art.

제2도는 본 발명에 따른 반도체 장치의 기준 전류 발생회로의 개념을 나타내는 것이다.2 shows the concept of the reference current generating circuit of the semiconductor device according to the present invention.

제3도는 본 발명에 따른 일실시예의 반도체 장치의 기준 전류 발생 회로를 나타내는 것이다.3 shows a reference current generating circuit of a semiconductor device of one embodiment according to the present invention.

제4도는 본 발명에 따른 반도체 장치의 기준전류 발생회로를 나타내는 것이다.4 shows a reference current generating circuit of the semiconductor device according to the present invention.

본 발명은 반도체 장치에 관한 것으로, 특히 반도체 장치의 기준전류 발생회로에 관한 것이다.The present invention relates to a semiconductor device, and more particularly, to a reference current generating circuit of a semiconductor device.

반도체 장치에서 사용되는 기준전류 회로는 외부의 환경에 무관하게 일정한 전류를 출력으로 내보내주어야 한다. 따라서, 기준전류 회로는 크게 두가지 특성을 가져야 한다. 첫째, 원하는 범위 내에서 인가해주는 전압의 변동에 관계없이 일정한 전류를 출력으로 내보내야 한다. 둘째, 원하는 범위내에서 외부온도 및 공정조건의 변화에 관계없이 일정한 전류를 출력으로 내보내야 한다.The reference current circuit used in the semiconductor device must send a constant current to the output regardless of the external environment. Therefore, the reference current circuit should largely have two characteristics. First, a constant current must be output to the output regardless of the voltage variation within the desired range. Second, a constant current must be output to the output regardless of changes in external temperature and process conditions within the desired range.

제1도는 종래의 반도체 장치의 기준전류 발생회로를 나타내는 것으로, PMOS 트랜지스터(PM1)에 흐르는 기준전류(Iref)는(A)으로써 나타내어지고, 여기에서, Vt,mn1은 NMOS트랜지스터(MN1)의 스레쉬홀드 전압을 나타낸다. 즉, 기준전류(Iref)는 NMOS트랜지스터(MN1)의 스레쉬홀드 전압(Vt)에 비례함을 알 수 있다.FIG. 1 shows a reference current generating circuit of a conventional semiconductor device. The reference current Iref flowing through the PMOS transistor PM1 is shown in FIG. Expressed as (A), where Vt, mn 1 represents the threshold voltage of the NMOS transistor MN1. That is, it can be seen that the reference current Iref is proportional to the threshold voltage Vt of the NMOS transistor MN1.

따라서, 기준전류(Iref)는 온도 및 공정 변화에 민감하게 변화하는 MOS트랜지스터(MN1)의 스레쉬홀드 전압에 따라서 변화하는 단점이 있었다.Therefore, the reference current Iref has a disadvantage in that it changes according to the threshold voltage of the MOS transistor MN1 that changes sensitively to temperature and process variations.

본 발명의 목적은 온도 및 공정 변화에 둔감한 기준전류 발생회로를 제공하는데 있다.An object of the present invention is to provide a reference current generation circuit insensitive to temperature and process changes.

이와 같은 목적을 달성하기 위하여 본 발명의 기준 전류 발생회로는 제1전압과 제2전압사이에 저항성분과 MOS트랜지스터로 구성되어 일정한 전압을 출력하는 전압발생수단과 상기 일정전압과 상기 제2전압사이에 저항성분과 MOS다이오우드를 연결하여 상기 일정전압을 상기 MOS트랜지스터의 스레쉬홀드전압을 뺀값을 상기 저항성분의 저항값으로 나눈 일정전류를 출력하는 것을 특징으로 한다.In order to achieve the above object, the reference current generating circuit of the present invention is composed of a resistance component and a MOS transistor between a first voltage and a second voltage and outputs a constant voltage between the constant voltage and the second voltage. A resistance current is connected to the MOS diode and a constant current is obtained by dividing the constant voltage by subtracting the threshold voltage of the MOS transistor by the resistance value of the resistance component.

첨부된 도면을 참고로하여 본 발명에 따른 기준전류 발생회로를 설명하기 전에 종래의 기준전류 발생회로를 설명하면 다음과 같다.Referring to the accompanying drawings, a conventional reference current generating circuit will be described before describing the reference current generating circuit according to the present invention.

제1도는 종래기술에 의한 기준전류 발생회로를 나타내는 것이다. 제1도에 있어서, 전원전압(Vcc)에 연결된 드레인전극과 접지전압(Vss)에 연결된 게이트 전극을 가지고 전류를 제한하는 PMOS트랜지스터(MP1)과, 전원전압(Vcc)에 연결된 드레인전극과 게이트전극과 공통 접속된 소오스전극을 가지며 전류를 제한하는 PMOS트랜지스터(MP2)와, 상기 PMOS트랜지스터(MP1)에 연결된 게이트전극과 상기 PMOS트랜지스터(MP2)의 소오스전극에 연결된 드레인전극을 가진 NMOS트랜지스터(MN2)와, 상기 NMOS트랜지스터(MN2)의 게이트전극에 연결된 드레인전극과 상기 NMOS트랜지스터(MN2)의 소오스전극에 연결된 게이트전극과 접지전압(Vss)에 연결된 소오스전극을 가진 NMOS트랜지스터(MN1)과, 상기 NMOS트랜지스터(MN1)의 게이트전극과 접지전압(Vss)사이에 연결된 저항(R1)로 구성되어 있다.1 shows a reference current generating circuit according to the prior art. 1, a PMOS transistor MP1 for limiting current with a drain electrode connected to the power supply voltage Vcc and a gate electrode connected to the ground voltage Vss, and a drain electrode and a gate electrode connected to the power supply voltage Vcc. A NMOS transistor (MN2) having a source electrode connected in common with the PMOS transistor (MP2) for limiting current, a gate electrode connected to the PMOS transistor (MP1), and a drain electrode connected to a source electrode of the PMOS transistor (MP2). And an NMOS transistor (MN1) having a drain electrode connected to the gate electrode of the NMOS transistor (MN2), a gate electrode connected to the source electrode of the NMOS transistor (MN2), and a source electrode connected to a ground voltage (Vss), and the NMOS. The resistor R 1 is connected between the gate electrode of the transistor MN1 and the ground voltage Vss.

여기에서, PMOS트랜지스터(MP2)를 통하여 흐르는 기준전류(Iref)를 식으로 나타내면 다음과 같다.Here, the reference current Iref flowing through the PMOS transistor MP2 is expressed as follows.

상기 식(1)로부터, 기준전류(Iref)는 NMOS트랜지스터(MN1)의 스레쉬홀드 전압에 비례한다.From Equation (1), the reference current Iref is proportional to the threshold voltage of the NMOS transistor MN1.

그래서, 기준전류(Iref)는 온도 및 공정 변화에 민감하게 변화하는 단점이 있었다.Thus, the reference current Iref has a disadvantage in that it is sensitive to changes in temperature and process.

제2도는 본 발명에 따른 기준전류 발생회로를 나타내는 것이다. 제2도에 있어서, 상기 저항(R1)에 연결된 게이트전극과 드레인전극과 접지전압에 연결된 소오스전극을 가진 NMOS트랜지스터(MN3)로 구성되어 있다.2 shows a reference current generating circuit according to the present invention. In FIG. 2, the NMOS transistor MN3 includes a gate electrode connected to the resistor R 1 , a drain electrode, and a source electrode connected to a ground voltage.

여기세서, PMOS트랜지스터(MP2)에 흐르는 기준전류(Iref)를 식으로 나타내면 다음과 같다.Here, the reference current Iref flowing through the PMOS transistor MP2 is expressed as follows.

식(2)로부터, 기준전류(Iref)는 NMOS트랜지스터(MN1)의 스레쉬홀드전압 값에서 NMOS트랜지스터(MN3)의 스레쉬홀드 전압을 뺀값에 비례한다. 그래서, 기준전류(Iref)는 온도 및 공정 변화에 둔감하게 변화한다.From Equation (2), the reference current Iref is proportional to the threshold voltage value of the NMOS transistor MN1 minus the threshold voltage of the NMOS transistor MN3. Thus, the reference current Iref changes insensitive to temperature and process changes.

제3도는 본 발명에 따른 실시예의 기준전류 발생회로를 나타내는 것이다.3 shows a reference current generating circuit of an embodiment according to the present invention.

제3도에 있어서, NMOS트랜지스터(MN1)과 NMOS트랜지스터(MN3)의 스레쉬홀드 전압의 차이를 주기위하여 NMOS트랜지스터(MN1)의 소오스 전극을 접지전압과 연결하고 기판(substrate)에 역 바이어스전압(vbb)을 인가하여 스레쉬홀드전압을 증가하고, NMOS트랜지스터(MN3)의 소오스 전극과 기판을 접지전압(Vss)에 연결하여 구성되어 있다.In FIG. 3, the source electrode of the NMOS transistor MN1 is connected to the ground voltage to provide a difference between the threshold voltages of the NMOS transistor MN1 and the NMOS transistor MN3, and the reverse bias voltage (or The threshold voltage is increased by applying vbb, and the source electrode and the substrate of the NMOS transistor MN3 are connected to the ground voltage Vss.

여기에서, PMOS트랜지스터(MP2)에 흐르는 기준전류(Iref)를 식으로 나타내면 다음과 같다.Here, the reference current Iref flowing through the PMOS transistor MP2 is expressed as follows.

식(3)으로부터, 기준전류(Iref)는 저항(R1)을 조절함에 따라 원하는 기준전류를 얻을 수 있다.From Equation (3), the reference current Iref can obtain a desired reference current by adjusting the resistance R 1 .

제4도는 본 발명에 따른 다른 실시예의 기준전류 발생회로를 나타내는 것이다. 제4도에 있어서, 저항(R1)에 연결된 드레인전극과, 게인트전극과 기판에 연결된 소오스를 가진 NMOS트랜지스터(MN5)와, 기판에 연결된 드레인전극과 접지전압에 연결된 게이트와 소오스를 가진 PMOS트랜지스터(MP3)으로 구성되어 있다. PMOS트랜지스터(MN1)의 경우, 소오스전압은 접지전압보다 PMOS트랜지스터의 스레쉬홀드전압 만큼 높게 되고 기판전압은 접지전압으로 하여 역바이어스 효과를 볼 수 있게 하였다. 따라서, PMOS트랜지스터(MP2)에 흐르는 전류는 NMOS트랜지스터 MN1과 MN5의 스레쉬홀드전압차에 비례하므로 온도와 공정 변화에 둔담한 기준전류 발생회로를 제공하게 된다.4 shows a reference current generating circuit of another embodiment according to the present invention. 4 Fig, resistance (R 1) and drain electrodes, PMOS's having a gate and a source connected to the NMOS transistor (MN5) having a source connected to the STE electrode and the substrate, a drain electrode and a ground voltage is connected to the board connected to the It consists of the transistor MP3. In the case of the PMOS transistor MN1, the source voltage is higher than the ground voltage by the threshold voltage of the PMOS transistor, and the substrate voltage is the ground voltage, so that the reverse bias effect can be seen. Therefore, the current flowing through the PMOS transistor MP2 is proportional to the threshold voltage difference between the NMOS transistors MN1 and MN5, thereby providing a reference current generation circuit that is dull with temperature and process changes.

여기에서, 제1도에 나타낸 종래의 회로와 제4도에 나타낸 본 발명의 회로의 온도에 따른 기준전류의 변화를 비교하면 다음과 같다.Here, the change of the reference current according to the temperature of the conventional circuit shown in FIG. 1 and the circuit of the present invention shown in FIG. 4 is as follows.

상기 표로부터 본 발명에 따른 회로가 종래의 회로에 비해 온도에 따른 기준전류의 변화가 작음을 알 수 있다. 따라서, 본 발명에 따른 회로는 좋은 기준전류 특성을 가진다. 본 발명에 따른 기준전류회로는 사용되는 반도체장치에 채용하여 제품의 신뢰성을 향상시킬 수 있다.From the table, it can be seen that the circuit according to the present invention has a smaller change in the reference current with temperature than the conventional circuit. Thus, the circuit according to the invention has good reference current characteristics. The reference current circuit according to the present invention can be employed in the semiconductor device used to improve the reliability of the product.

Claims (7)

제1전압과 제2전압사이에 저항성분과 MOS트랜지스터로 구성되어 일정한 전압을 출력하는 전압발생 수단과 상기 일정전압과 상기 제2전압사이에 저항성분과 MOS다이오우드를 연결하여 상기 일정전압을 상기 MOS트랜지스터의 스레쉬홀드전압을 뺀값을 상기 저항성분의 저항값으로 나눈 일정전류를 출력하는 것을 특징으로 하는 기준전류회로.A voltage generating means configured to output a constant voltage between the first voltage and the second voltage, and to connect the resistance component and the MOS diode between the constant voltage and the second voltage, and convert the constant voltage of the MOS transistor. A reference current circuit, comprising: outputting a constant current obtained by dividing a value obtained by subtracting a threshold hold voltage by a resistance value of the resistance component. 제1항에 있어서, 상기 전압발생수단은 제1전압에 연결된 소오스전극과 제2전압에 연결된 게이트전극을 가진 제1MOS트랜지스터; 상기 제1MOS트랜지스터의 드레인전극에 연결된 드레인전극과 제2전압에 연결된 소오스전극을 가진 제2MOS트랜지스터; 제1전압에 연결된 소오스전극과 드레인전극과 공통연결된 소오스전극을 가진 제3MOS트랜지스터; 상기 제3MOS트랜지스터의 게이트전극에 연결된 드레인전극과 상기 제2MOS트랜지스터의 드레인전극에 연결된 게이트전극과 상기 제2MOS트랜지스터의 게이트전극에 연결된 소오스전극을 가진 제4MOS트랜지스터로 구성된 것을 특징으로 하는 기준전류회로.2. The voltage generator of claim 1, wherein the voltage generator comprises: a first MOS transistor having a source electrode connected to a first voltage and a gate electrode connected to a second voltage; A second MOS transistor having a drain electrode connected to the drain electrode of the first MOS transistor and a source electrode connected to a second voltage; A third MOS transistor having a source electrode connected to the first voltage and a source electrode connected to the drain electrode in common; And a fourth MOS transistor having a drain electrode connected to the gate electrode of the third MOS transistor, a gate electrode connected to the drain electrode of the second MOS transistor, and a source electrode connected to the gate electrode of the second MOS transistor. 제1항에 있어서, 상기 MOS다이오우드수단은 상기 저항수단에 연결된 드레인전극과 게이트전극과 상기 제2전압에 연결된 소오스전극을 가진 것을 특징으로 하는 기준전류회로.The reference current circuit according to claim 1, wherein the MOS diode means has a drain electrode connected to the resistance means, a gate electrode, and a source electrode connected to the second voltage. 제1항에 있어서, 상기 MOS다이오우드수단은 상기 저항수단에 연결된 드레인전극과 게이트전극과 상기 제2전압과 기판에 연결된 소오스전극을 가진 것을 특징으로 하는 기준전류회로.The reference current circuit according to claim 1, wherein the MOS diode means has a drain electrode and a gate electrode connected to the resistance means, and a source electrode connected to the second voltage and the substrate. 제1항에 있어서, 상기 MOS다이오우드수단은 상기 저항수단에 연결된 소오스전극과 게이트전극을 가진 제1NMOS트랜지스터과 상기 제1NMOS트랜지스터의 소오스전극과 기판에 연결된 소오스전극과 제2전압에 연결된 드레인전극과 게이트전극을 가진 제2PMOS트랜지스터로 구성된 것을 특징으로 하는 기준전류회로.The semiconductor device of claim 1, wherein the MOS diode means comprises: a first NMOS transistor having a source electrode and a gate electrode connected to the resistance means, a source electrode of the first NMOS transistor, a source electrode connected to a substrate, and a drain electrode and a gate electrode connected to a second voltage; A reference current circuit comprising a second PMOS transistor having a. 제1항에 있어서, 상기 일정전압이 상기 MOS다이오우드수단의 스레쉬홀드전압보다 큰 것을 특징으로 하는 기준전류회로.The reference current circuit according to claim 1, wherein the constant voltage is larger than the threshold voltage of the MOS diode means. 제1항에 있어서, 상기 일정전압이 상기 MOS다이오우드수단의 스레쉬홀드전압 차이를 역 바이어스전압 차이로 조절하는 것을 특징으로 하는 기준전류회로.2. The reference current circuit according to claim 1, wherein the constant voltage adjusts a difference in threshold voltage of the MOS diode means to a difference in reverse bias voltage.
KR1019920004658A 1992-03-20 1992-03-20 Reference current generating circuit KR940005510B1 (en)

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Application Number Priority Date Filing Date Title
KR1019920004658A KR940005510B1 (en) 1992-03-20 1992-03-20 Reference current generating circuit
FR9205216A FR2688903B1 (en) 1992-03-20 1992-04-28 REFERENCE CURRENT GENERATION CIRCUIT.
CN92103104A CN1065532A (en) 1992-03-20 1992-04-28 Reference current generating circuit
ITMI921016A IT1254947B (en) 1992-03-20 1992-04-29 REFERENCE CURRENT GENERATOR CIRCUIT
DE4214403A DE4214403A1 (en) 1992-03-20 1992-04-30 REFERENCE CURRENT GENERATOR CIRCUIT
GB9209400A GB2265479A (en) 1992-03-20 1992-04-30 Reference current generating circuit
JP4123528A JPH0675648A (en) 1992-03-20 1992-05-15 Reference-current generating circuit

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FR2829248B1 (en) * 2001-09-03 2004-08-27 St Microelectronics Sa CURRENT GENERATOR FOR LOW SUPPLY VOLTAGE
KR100588339B1 (en) 2004-01-07 2006-06-09 삼성전자주식회사 Current reference circuit with voltage-current converter having auto-tuning function
JP4932322B2 (en) * 2006-05-17 2012-05-16 オンセミコンダクター・トレーディング・リミテッド Oscillator circuit
JP4989106B2 (en) * 2006-05-17 2012-08-01 オンセミコンダクター・トレーディング・リミテッド Oscillator circuit
JP5771489B2 (en) * 2011-09-15 2015-09-02 ルネサスエレクトロニクス株式会社 Semiconductor device
CN102385409B (en) * 2011-10-14 2013-12-04 中国科学院电子学研究所 VGS/R (Voltage Gradient Standard/Reference) type reference source capable of supplying zero-temperature coefficient voltage and current reference at the same time
JP6292901B2 (en) * 2014-01-27 2018-03-14 エイブリック株式会社 Reference voltage circuit
CN107666143B (en) * 2016-07-27 2019-03-22 帝奥微电子有限公司 Negative pressure charge pump circuit
CN106774593A (en) * 2016-12-29 2017-05-31 北京兆易创新科技股份有限公司 A kind of current source
CN107015594A (en) * 2017-05-30 2017-08-04 长沙方星腾电子科技有限公司 A kind of bias current generating circuit

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DE4214403A1 (en) 1993-09-23
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KR930020847A (en) 1993-10-20
FR2688903A1 (en) 1993-09-24
ITMI921016A1 (en) 1993-10-29
GB2265479A (en) 1993-09-29
ITMI921016A0 (en) 1992-04-29
IT1254947B (en) 1995-10-11
GB9209400D0 (en) 1992-06-17
FR2688903B1 (en) 1994-06-03

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