CN103235631B - Voltage stabilizer circuit - Google Patents
Voltage stabilizer circuit Download PDFInfo
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- CN103235631B CN103235631B CN201310129073.6A CN201310129073A CN103235631B CN 103235631 B CN103235631 B CN 103235631B CN 201310129073 A CN201310129073 A CN 201310129073A CN 103235631 B CN103235631 B CN 103235631B
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- nmos tube
- clamping circuit
- drain terminal
- source
- pmos
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Abstract
The invention relates to the technical field of simulation power supplies, in particular to a voltage stabilizer circuit which is simple in structure and small in area and greatly reduces cost. The voltage stabilizer circuit comprises a power supply Voltage Drain Drain (VDD) and a resistor R1 and is characterized by further comprising a first clamping circuit, a second clamping circuit and a first N-channel Metal Oxide Semiconductor (NMOS) tube. The first clamping circuit comprises a second NMOS tube and a resistor R2. The drain end of the second NMOS tube is connected with the grid end of the first NMOS tube and one end of the resistor R2 respectively, and the grid end of the second NMOS tube is connected with the other end of the resistor R2 and one end of the resistor R1 respectively. The other end of the resistor R1 is connected with the power supply VDD and the drain end of the first NMOS tube. The source end of the first NMOS tube is connected with the voltage output end. The second clamping circuit comprises an NMOS tube with the grid end connected with the drain end. The source end of the second NMOS tube is connected with the drain end of the NMOS tube, and the source end of the NMOS tube is grounded.
Description
Technical field
The present invention relates to analog power technical field, be specially a kind of voltage-stabiliser circuit.
Background technology
In general open-loop voltage stabilizing circuit, frequent employing PMOS is as driving circuit, as shown in Figure 1, when driving same current, its circuit area is more than 2.5 times of NMOS tube, simultaneously more than in the high-voltage applications of more than 12V, the device and the technique that use rear grid sample must be needed, thus cause the further increase of area and workpiece more complicated, meanwhile, adopt PMOS time, also need in circuit to include reference voltage source and error amplifier, whole circuit area is large, and complex structure, cost of manufacture is high.
Summary of the invention
In order to solve the problem, the invention provides a kind of voltage-stabiliser circuit, its circuit structure is simple, and area is little, and cost reduces greatly.
Its technical scheme is such: a kind of voltage-stabiliser circuit, it comprises power vd D, resistance R1, it is characterized in that, it also comprises the first clamping circuit, second clamping circuit, first NMOS tube, described first clamping circuit comprises the second NMOS tube and resistance R2, the drain terminal of described second NMOS tube connects the grid end of the first NMOS tube and described resistance R2 one end respectively, grid end connects the described resistance R2 other end and described resistance R1 one end respectively, the described resistance R1 other end connects the drain terminal of described power vd D and described first NMOS tube respectively, the source of described first NMOS tube connects voltage output end, described second clamping circuit comprises the NMOS tube that grid end is connected with drain terminal, the source of described second NMOS tube connects the drain terminal of described NMOS tube, the source ground connection of described NMOS tube.
It is further characterized in that, also PMOS is comprised between the NMOS tube of described second clamping circuit and the second NMOS tube of described first clamping circuit, the grid end of described PMOS is connected with drain terminal, the source of described PMOS is connected with the source of described second NMOS tube, drain terminal is connected with the drain terminal of the NMOS tube in described second clamping circuit, the source ground connection of described NMOS tube; Multiple described PMOS series connection can be comprised in described second clamping circuit; Multiple described NMOS tube series connection can be comprised in described second clamping circuit; Described second clamping circuit comprises the 3rd, the 4th PMOS of two series connection, 5th, the 6th, the 7th, the 8th NMOS tube of four series connection, the source of described 3rd PMOS is connected with the source of described second NMOS tube, the drain terminal of described 4th PMOS is connected with the drain terminal of described 5th NMOS tube, the source ground connection of described 8th NMOS tube; The NMOS tube of described second clamping circuit, PMOS mostly are ten series connection respectively most.
After adopting structure of the present invention, the first NMOS tube, the first clamping circuit and the second clamping circuit is only included in circuit, without the need to reference voltage source and error amplifier after employing NMOS tube, reduce the area of circuit, simultaneously circuit of the present invention can be applied in a wider voltage range, when the high-voltage applications more than 12V, overcomes in prior art and needs to use the rear device of grid sample and the defect of technique, further reduce area and simplify circuit structure simultaneously, cost reduces greatly.
Accompanying drawing explanation
Fig. 1 is prior art circuits figure;
Fig. 2 is first embodiment of the invention circuit diagram;
Fig. 3 is second embodiment of the invention circuit diagram.
Embodiment
As shown in Figure 2, a kind of voltage-stabiliser circuit, it comprises power vd D, resistance R1, it also comprises the first clamping circuit, second clamping circuit, first NMOS tube MN1, first clamping circuit comprises the second NMOS tube MN2 and resistance R2, the drain terminal of the second NMOS tube MN2 connects grid end and resistance R2 one end of the first NMOS tube MN1 respectively, grid end is the contact resistance R2 other end and resistance R1 one end respectively, the resistance R1 other end connects the drain terminal of power vd D and the first NMOS tube MN1 respectively, the source of the first NMOS tube MN1 connects voltage output end Vout, second clamping circuit comprises the 5th NMOS tube MN5 that grid end is connected with drain terminal, the source of the second NMOS tube MN2 connects the drain terminal of the 5th NMOS tube MN5, the source ground connection GND of the 5th NMOS tube MN5.
Also PMOS is comprised between 5th NMOS tube MN5 of the second clamping circuit and the second NMOS tube MN2 of the first clamping circuit, the grid end of PMOS is connected with drain terminal, the source of PMOS is connected with the source of the second NMOS tube MN2, drain terminal is connected with the drain terminal of the 5th NMOS tube MN5 in the second clamping circuit, the series connection of multiple PMOS can be comprised in second clamping circuit, the series connection of multiple NMOS tube in the second clamping circuit, can be comprised.As shown in Figure 3, the be connected in series the 3rd is also comprised between 5th NMOS tube MN5 of the second clamping circuit and the second NMOS tube MN2 of the first clamping circuit, 4th PMOS MP3, MP4, 3rd, 4th PMOS MP3, the grid end of MP4 is connected with drain terminal, the source of the 3rd PMOS MP3 is connected with the source of the second NMOS tube MN2, the drain terminal of the 4th PMOS MP4 is connected with the drain terminal of the 5th NMOS tube MN5, the drain terminal series connection of the 5th NMOS tube MN5 is sequentially connected in series the 6th, 7th, 8th NMOS tube MN6, MN7, MN8, the source ground connection GND of the 8th NMOS tube MN8, now can obtain more stable output voltage, the NMOS tube of the second clamping circuit, PMOS mostly are ten series connection respectively most, and connect in the second clamping circuit multiple NMOS tube or PMOS, can increase the stability of circuit, but easily make circuit area excessive when connecting too much, more complicated circuit structure.
Claims (2)
1. a voltage-stabiliser circuit, it comprises power vd D, resistance R1, it is characterized in that, it also comprises the first clamping circuit, second clamping circuit, first NMOS tube, described first clamping circuit comprises the second NMOS tube and resistance R2, the drain terminal of described second NMOS tube connects the grid end of the first NMOS tube and described resistance R2 one end respectively, grid end connects the described resistance R2 other end and described resistance R1 one end respectively, the described resistance R1 other end connects the drain terminal of described power vd D and described first NMOS tube respectively, the source of described first NMOS tube connects voltage output end, described second clamping circuit comprises the NMOS tube that grid end is connected with drain terminal, the source of described second NMOS tube connects the drain terminal of described NMOS tube, the source ground connection of described NMOS tube, also PMOS is comprised between the NMOS tube of described second clamping circuit and the second NMOS tube of described first clamping circuit, the grid end of described PMOS is connected with drain terminal, and the source of described PMOS is connected with the source of described second NMOS tube, drain terminal is connected with the drain terminal of the NMOS tube in described second clamping circuit, described second clamping circuit comprises the 3rd, the 4th PMOS of two series connection, 5th, the 6th, the 7th, the 8th NMOS tube of four series connection, the source of described 3rd PMOS is connected with the source of described second NMOS tube, the drain terminal of described 4th PMOS is connected with the drain terminal of described 5th NMOS tube, the source ground connection of described 8th NMOS tube.
2. a voltage-stabiliser circuit, it comprises power vd D, resistance R1, it is characterized in that, it also comprises the first clamping circuit, second clamping circuit, first NMOS tube, described first clamping circuit comprises the second NMOS tube and resistance R2, the drain terminal of described second NMOS tube connects the grid end of the first NMOS tube and described resistance R2 one end respectively, grid end connects the described resistance R2 other end and described resistance R1 one end respectively, the described resistance R1 other end connects the drain terminal of described power vd D and described first NMOS tube respectively, the source of described first NMOS tube connects voltage output end, described second clamping circuit comprises the NMOS tube that grid end is connected with drain terminal, the source of described second NMOS tube connects the drain terminal of described NMOS tube, the source ground connection of described NMOS tube, also PMOS is comprised between the NMOS tube of described second clamping circuit and the second NMOS tube of described first clamping circuit, the grid end of described PMOS is connected with drain terminal, and the source of described PMOS is connected with the source of described second NMOS tube, drain terminal is connected with the drain terminal of the NMOS tube in described second clamping circuit, described second clamping circuit comprises multiple described PMOS series connection, described second clamping circuit comprises multiple described NMOS tube series connection, the NMOS tube of described second clamping circuit, PMOS mostly are ten series connection respectively most.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310129073.6A CN103235631B (en) | 2013-04-15 | 2013-04-15 | Voltage stabilizer circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310129073.6A CN103235631B (en) | 2013-04-15 | 2013-04-15 | Voltage stabilizer circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103235631A CN103235631A (en) | 2013-08-07 |
| CN103235631B true CN103235631B (en) | 2015-07-08 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201310129073.6A Active CN103235631B (en) | 2013-04-15 | 2013-04-15 | Voltage stabilizer circuit |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3335337B1 (en) * | 2015-08-10 | 2023-06-07 | Finisar Corporation | Out-of-band signal detection |
| CN107066007B (en) * | 2017-05-09 | 2018-08-10 | 普冉半导体（上海）有限公司 | A kind of voltage-stabiliser circuit |
| CN107170420B (en) * | 2017-07-12 | 2022-07-26 | 深圳市航顺芯片技术研发有限公司 | Circuit structure for driving bias voltage of LCD |
| CN108847836A (en) * | 2018-08-10 | 2018-11-20 | 深圳南云微电子有限公司 | Electrostatic discharge self-protection circuit and self-protection method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6040735A (en) * | 1996-09-13 | 2000-03-21 | Samsung Electronics Co., Ltd. | Reference voltage generators including first and second transistors of same conductivity type |
| CN101751061A (en) * | 2008-12-17 | 2010-06-23 | 上海华虹Nec电子有限公司 | High voltage stabilizer and high voltage intrinsic NMOS tube |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2763531B2 (en) * | 1986-10-13 | 1998-06-11 | 松下電器産業株式会社 | MOS constant voltage circuit |
| GB2259376A (en) * | 1991-08-24 | 1993-03-10 | Motorola Gmbh | Voltage and current reference source |
| JP3586502B2 (en) * | 1995-09-04 | 2004-11-10 | 株式会社ルネサステクノロジ | Voltage generation circuit |
| JP2002074967A (en) * | 2000-08-29 | 2002-03-15 | Mitsubishi Electric Corp | Step-down power-supply circuit |
| CN101853041A (en) * | 2010-03-26 | 2010-10-06 | 东莞电子科技大学电子信息工程研究院 | High-voltage pre-regulation voltage reduction circuit for use in wide input range |
-
2013
- 2013-04-15 CN CN201310129073.6A patent/CN103235631B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6040735A (en) * | 1996-09-13 | 2000-03-21 | Samsung Electronics Co., Ltd. | Reference voltage generators including first and second transistors of same conductivity type |
| CN101751061A (en) * | 2008-12-17 | 2010-06-23 | 上海华虹Nec电子有限公司 | High voltage stabilizer and high voltage intrinsic NMOS tube |
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| CN103235631A (en) | 2013-08-07 |
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Inventor after: Zhou Ping Inventor after: Li Zhaogui Inventor after: Wang Nan Inventor before: Li Zhaogui |
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Free format text: CORRECT: INVENTOR; FROM: LI ZHAOGUI TO: ZHOU PING LI ZHAOGUI WANG NAN |
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Effective date of registration: 20160722 Address after: 200000 Shanghai City, Pudong New Area Chinese Jing (Shanghai) Free Trade Zone No. 351 Building No. 2 room A676-22 Patentee after: Pu ran semiconductor (Shanghai) Co., Ltd. Address before: 214102 Jiangsu province Wuxi city Xishan District Furong Road No. 99 three six 716 zuiun Patentee before: Wuxi Puya Semiconductor Co., Ltd. |
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Address after: Room 504, 560 Shengxia Road, Pudong New Area, Shanghai 200000 Patentee after: Praran semiconductor (Shanghai) Co., Ltd Address before: 200000 Shanghai City, Pudong New Area Chinese Jing (Shanghai) Free Trade Zone No. 351 Building No. 2 room A676-22 Patentee before: PUYA SEMICONDUCTOR (SHANGHAI) Co.,Ltd. |