JPS6396927A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6396927A JPS6396927A JP24250186A JP24250186A JPS6396927A JP S6396927 A JPS6396927 A JP S6396927A JP 24250186 A JP24250186 A JP 24250186A JP 24250186 A JP24250186 A JP 24250186A JP S6396927 A JPS6396927 A JP S6396927A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- silicon
- film
- implanted
- silicon substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 238000004519 manufacturing process Methods 0.000 title claims description 3
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 9
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims abstract description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract 4
- 239000007789 gas Substances 0.000 claims abstract 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract 2
- 229910021529 ammonia Inorganic materials 0.000 claims abstract 2
- 239000001257 hydrogen Substances 0.000 claims abstract 2
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract 2
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract 2
- 229910052710 silicon Inorganic materials 0.000 claims description 32
- 239000010703 silicon Substances 0.000 claims description 32
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 25
- -1 silicon ions Chemical class 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 abstract description 6
- 238000007254 oxidation reaction Methods 0.000 abstract description 6
- 150000002500 ions Chemical class 0.000 abstract 2
- 230000003064 anti-oxidating effect Effects 0.000 abstract 1
- 150000004767 nitrides Chemical class 0.000 description 6
- 239000010410 layer Substances 0.000 description 5
- 230000002265 prevention Effects 0.000 description 4
- 238000002513 implantation Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- WTDRDQBEARUVNC-LURJTMIESA-N L-DOPA Chemical compound OC(=O)[C@@H](N)CC1=CC=C(O)C(O)=C1 WTDRDQBEARUVNC-LURJTMIESA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000002316 cosmetic surgery Methods 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、高速に成長させたシリコン基板直接熱窒化膜
をＭＩＳＦＥＴのゲート絶縁膜あるいは、各種半導体装
置の選択酸化防止膜として使用する半導体装置の製造方
法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is directed to the manufacture of semiconductor devices in which a rapidly grown direct thermal nitride film on a silicon substrate is used as a gate insulating film of a MISFET or a selective oxidation prevention film of various semiconductor devices. It is about the method.
従来の技術
従来のシリコン基板の直接熱窒化においては、窒化膜の
成長速度が遅い之め、実用的成長時間内に得られる膜厚
は、数十ム程度（アンモニアガス中、１１５０’Ｃ，１
時間で約４０ム）であり、これを利用した半導体装置は
主流ではなかった。Prior Art In conventional direct thermal nitridation of silicon substrates, the growth rate of the nitride film is slow, so the film thickness obtained within a practical growth time is about several tens of micrometers (in ammonia gas, 1150'C, 1
(approximately 40 μm per hour), and semiconductor devices using this were not mainstream.
発明が解決しようとする問題点
本発明は、シリコン基板の直接熱窒化における遅い成長
速度を解決するものである。Problems to be Solved by the Invention The present invention solves the slow growth rate in direct thermal nitridation of silicon substrates.
問題点を解決するための手段
本発明は、前記問題点を解決するため、シリコン基板表
面へのシリコンイオン注入、適切なアニール、にひきつ
づいて、シリコン基板の直接熱窒化をおこなうものであ
る。Means for Solving the Problems In order to solve the above-mentioned problems, the present invention involves implanting silicon ions into the surface of the silicon substrate, appropriate annealing, and then directly thermal nitriding the silicon substrate.
作用
本発明は、前記手順をとることにより、シリコン基板の
直接熱窒化速度を向上させるものである。Operation The present invention improves the rate of direct thermal nitridation of silicon substrates by taking the above steps.
シリコン基板に、シリコンイオン注入し、適切にアニー
ルすると、シリコン基板の表面付近に格子間シリコンの
多量に含まれる層を作ることができる。また、シリコン
基板の直接熱窒化速度は、この格子間シリコンの存在に
よって増速される。When a silicon substrate is implanted with silicon ions and properly annealed, an interstitial silicon-rich layer can be created near the surface of the silicon substrate. Also, the direct thermal nitridation rate of the silicon substrate is increased by the presence of this interstitial silicon.
従って、シリコン基板表面にシリコンを注入し。Therefore, silicon is implanted onto the surface of the silicon substrate.
適切にアニールすれば、このシリコン基板表面は、速い
窒化速度で直接熱窒化さｎる。If properly annealed, this silicon substrate surface can be thermally nitrided directly with a fast nitridation rate.
実施例 以下本発明の一実施例について図面と共に説明する。Example An embodiment of the present invention will be described below with reference to the drawings.
第１図において、シリコン基板１にシリコンをイオン注
入２（例えば、７０ＫＩＳＶ、 １０ ｃｍ ） し
たのち、適切なアニールをおこなうと、第２図に示すよ
うにシリコン基板表面近傍（先の条件では約０．１μ）
に、格子間シリコンが高濃度に存在する層３ができる。In FIG. 1, when silicon is ion-implanted 2 (e.g., 70 KISV, 10 cm) into a silicon substrate 1 and then an appropriate annealing is performed, as shown in FIG. .1μ)
A layer 3 containing a high concentration of interstitial silicon is formed.
この層は、シリコン基板の直接熱窒化速度を増速する。This layer increases the rate of direct thermal nitridation of the silicon substrate.
前記処理を通じて得られたシリコン基板の直接熱窒化膜
４を絶縁膜、あるいは、選択酸化用の酸化防止膜として
用いる。第４図は、このようにして成長させたシリコン
熱窒化膜４をＬＯＣＯ８分離法によるＭＩＳＦＲＴに応
用した場合の実施例であり、本発明によるシリコン熱窒
化膜は、ＬＯＧＯ８分離形成時の選択酸化用酸化防止膜
として、さらにＭＩＳＦＩＣＴのゲート絶縁膜として使
用している。ここで、第４図の５は、ＬＯＧＯ８分離の
素子間分離酸化膜、同図、６はポリシリコンゲート電極
、同図、７はへ用不純物注入領域、同図、８は層間絶縁
膜、同図、９はアルミ配線である。The direct thermal nitride film 4 of the silicon substrate obtained through the above treatment is used as an insulating film or an oxidation prevention film for selective oxidation. FIG. 4 shows an example in which the silicon thermal nitride film 4 grown in this manner is applied to MISFRT using the LOCO8 separation method. It is used as an oxidation prevention film and as a gate insulating film for MISFICT. Here, 5 in FIG. 4 is an inter-element isolation oxide film for LOGO8 isolation, 6 in the same figure is a polysilicon gate electrode, 7 is an impurity implantation region in the same figure, 8 is an interlayer insulating film, Figure 9 shows aluminum wiring.
発明の効果
本発明によれば、きわめて簡易な処理により、シリコン
基板の直接熱窒化速度を向上させることが可能であシ、
半導体装置に用いられる絶縁膜、基板酸化防止膜の形成
法として、実用的にきわめて有用である。Effects of the Invention According to the present invention, it is possible to improve the direct thermal nitridation rate of a silicon substrate through extremely simple processing.
This method is extremely useful for forming insulating films and substrate oxidation prevention films used in semiconductor devices.
第１図〜３図は本発明の一実施例方法を説明するための
工程断面図、第４図は本発明の方法を利用して作成した
ＭＩＳＦＥＴの断面図である。
１・・・・・・シリコン基板、２・・・・・・シリコン
注入層、３・・・・・・シリコンイオン注入層、４・・
・・・・シリコン熱窒化膜、６・・・・・・ＬＯＣＯ８
分離、６・・・・・・ポリシリコンゲート電極、７・・
・・・・Ｓ／Ｄ用不純物注入域、８・・・・・・層間絶
縁膜、９・・・・・・ムｌ配線。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
Ｉ ↓ ↓
一一一１゛
一一一上。
第２図
一□−一り
第３図
一一一一」
テ
！−シリコン基１次
２−シリコンテ上滲コ１
ゝ２
シリコン熱窒化膜Ｅ４
４−ｊｌｉ襖しか一記υｔ
、！；−ＬＯＣＯｊａｌｌ
８−、ｌＦＪ’！塑ミ別ドパ県。
デーＭ酉シリに1 to 3 are process cross-sectional views for explaining an embodiment of the method of the present invention, and FIG. 4 is a cross-sectional view of a MISFET manufactured using the method of the present invention. 1... Silicon substrate, 2... Silicon implanted layer, 3... Silicon ion implanted layer, 4...
...Silicon thermal nitride film, 6...LOCO8
Separation, 6...Polysilicon gate electrode, 7...
. . . S/D impurity implantation region, 8 . . . Interlayer insulating film, 9 . . . Mulit wiring. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure I ↓ ↓ 1111゛111 above. Figure 2 1□-1 Figure 3 1111” Te! -Silicon base primary 2-Silicon base 1 ゝ2 Silicon thermal nitride film E4 4-jli Fusuma or one note υt,! ;-LOCOjall 8-, lFJ'! Dopa prefecture by plastic surgery. Day M Toshiri
Claims (1)
なアニール処理を加えた後、清浄なアンモニアもしくは
、窒素／水素混合ガス中でシリコン基板の直接熱窒化を
するようにした半導体装置の製造方法。A method for manufacturing a semiconductor device, in which silicon ions are implanted into the surface of a Si substrate, followed by appropriate annealing treatment, and then the silicon substrate is directly thermally nitrided in clean ammonia or a nitrogen/hydrogen mixed gas.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24250186A JPS6396927A (en) | 1986-10-13 | 1986-10-13 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24250186A JPS6396927A (en) | 1986-10-13 | 1986-10-13 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6396927A true JPS6396927A (en) | 1988-04-27 |
Family
ID=17090032
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24250186A Pending JPS6396927A (en) | 1986-10-13 | 1986-10-13 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6396927A (en) |
-
1986
- 1986-10-13 JP JP24250186A patent/JPS6396927A/en active Pending
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