JPS6394362A - Bus coupling device - Google Patents

Abstract

PURPOSE:To contrive to shorten a waiting time, by providing a means which recognizes whether an interrupt request is approved or neglected, at the time of executing an interrupt request instruction. CONSTITUTION:A coupling device 1 which performs an interrupt operation to a central processor connected to an opposite system bus is inserted between a first common input/output bus 3 and a second common input/output bus 5. The coupling device 1 sends out a waiting response to the central processor executing an input/output put instruction through the common input/output bus while it is in a state waiting response for the interrupt request to the central processor of the opposite system, and when the response for the interrupt request is issued, it is synchronized with the responding operation of the input/output instruction. Furthermore, the storage of an interrupt waiting state is reset by a synchronized response for the interrupt request, and also, the response corresponding to a responding content from the central processor of the opposite system is performed for the input/output instruction.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to interrupt control means between central processing units.

〔overview〕

The present invention provides means for recognizing whether an interrupt request is approved or rejected at the time when an interrupt request command is executed in the interrupt control means between central processing units, thereby reducing the time required to recognize the time when the interrupt request is approved or rejected. This reduces hardware and software requirements and reduces waiting time.

[Conventional technology]

As interrupt control means between central processing units, there are methods in which separate interfaces are provided between central processing units, and methods in which a device for coupling common input/output buses is used to implement input/output commands. The present invention relates to the latter. By the way, the central processing unit does not immediately start processing even if there is an interrupt request, but it has a processing priority, and the processing priority of the interrupt request is that the central processing unit that processed it when the request was made If the value is higher than that, the interrupt request will be processed immediately, but if it is lower, the interrupt request will be placed in a waiting state. Here, there are two types: one type that notifies the request source of the response of approval or rejection to the interrupt request, and the other type that does not notify the request source. The present invention relates to the former.

The configuration of this type of conventional device is shown in FIGS. 6 to 8, and the operating sequence is shown in FIG. 9. When an interrupt request is made from the first CPU 2 to the second CPU 4, when an input/output command for the other system CPU interrupt request is executed to the coupling device 1', the interrupt request is sent via the first common input/output bus 3. coupling device 1
' will be notified. The A unit 6' of the coupling device 1' determines that the destination of the bus transfer is directed to itself, captures the bus transfer, and decodes the contents of the input/output command. The content is the other CPU
If it is an interrupt request to the coupling device 1', it is notified to the B section 7' of the coupling device 1', and the first CPU 2 is notified of the interrupt request to the coupling device 1'.
An approval bus response is sent via the first common input/output bus 3 to notify that the input/output command has been successfully executed. The B section 7' of the coupling device 1' issues an interrupt request to the second CPU 4 via the second common input/output bus 5. When the interrupt request is accepted and there is a bus response of approval from the second CPU 4 via the second common input/output bus 5, the series of interrupt operations is completed. If there is a rejection bus response based on the processing priority, the B section 7' of the coupling device 1' enters a waiting state.

There are two types of cancellation of this waiting state: one in which the waiting state is canceled after a certain period of time has elapsed, and one in which a notification of cancellation is received from the central processing unit. When the wait state is released, the above-mentioned B unit 7' again issues an interrupt request to the second CPU 4 via the second common input/output bus 5. Thereafter, the above operations are repeated until the request is accepted by the second CPtJ4, that is, until an approval bus response is received.

Furthermore, since the coupling device 1' has a symmetrical circuit configuration when viewed from the first common input/output bus 3 and the second common input/output bus 5, The above-mentioned operation is also performed when a request is made.

[Problem that the invention seeks to solve]

In such conventional coupling devices, in order to maintain the order of processing, a separate means is required for the central processing unit that made the request to know the time when the interrupt request to the other system's central processing unit was accepted. There is a drawback that.

For example, a storage device or register that can be accessed by both central processing units may be provided, and the contents may be periodically read out to determine whether the other party has accepted the data. There are methods to do this, but all of them have drawbacks such as requiring a large amount of hardware circuitry for recognition, and increasing software overhead, reducing processing speed.

In addition, when analyzing failures caused by hardware or software, such as loss of interrupt requests, rear-end collisions, or errors, it is important to note that the processing of the two central processing units is asynchronous, and that the coupling device Waiting until the problem is approved by the government causes a long time to elapse between the time when the cause of the problem occurs and the time when the failure is recognized, which has the disadvantage of being extremely difficult.

The present invention aims to eliminate such drawbacks, and aims to provide a bus coupling device that can reduce the amount of hardware and software required to recognize the time of acceptance or rejection, and shorten waiting time. do.

[Means for solving problems]

The present invention provides an intervening path between an input/output bus to which one central processing unit is connected and an input/output bus to which the other central processing unit is connected, and an interrupt request from the one central processing unit. In the bus coupling device, the bus coupling device is provided with a notification means for notifying the one central processing unit of the approval or rejection response of the other central processing unit to the other central processing unit, means for repeatedly sending a signal indicating this state to one central processing unit over a period of waiting for a response from the processing unit; and when the other central processing unit responds with approval or rejection, the timing of this response and one of the abovementioned central processing units; means for synchronizing the timing of the interrupt request of the central processing unit of the central processing unit, and sending a response of approval or rejection from the other central processing unit to the one central processing unit based on the synchronized interrupt request. The invention is characterized by comprising a means for doing so.

[Effect]

While waiting for a response to an interrupt request to the partner central processing unit, a waiting response is sent to the central processing unit that executed the input/output command via the common input/output bus.

When there is a response to an interrupt request, it is synchronized with the response operation of the input/output command. The interrupt wait state memory is reset in response to a synchronized interrupt request, and a response is made to an input/output command according to the response content from the partner central processing unit.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a block configuration diagram showing the configuration of the embodiment system, in which a coupling device 1 that performs an interrupt operation on a central processing unit connected to a partner system bus has a first common input/output bus 3 and a second common input/output bus 3. is inserted between the common input/output bus 5 and the common input/output bus 5. Further, FIGS. 2 and 3 are block diagrams showing the configuration of the coupling device 1 of FIG. 1. FIG. 4 is a sequence diagram showing the operation of this embodiment system.

Since the circuit configurations of the A part and the B part are symmetrical with respect to each common input/output bus, here, from the first CPU 2 to the second
The interrupt operation by input/output commands to the CPU 4 will be explained.

First, data transfer on a common input/output bus for transferring destination device addresses, command signals, data transmission, and response signals in a conversational manner will be explained with reference to FIG. When transferring data between devices connected to a common bus, first, the right to use the bus is established, and then the destination device address and data transfer information are sent to the address bus C in synchronization with the address and data transmission control signal A. A command signal E indicating an attribute is sent to the common bus. In the case of data output, output data is output to the common bus in synchronization with the control signal A to the data bus D. Each device connected to the common bus decodes the destination device address on address bus C as control signal A changes from false to true, and if it is its own address, it outputs command signal E and data. For example, it takes in the contents of the data bus D, changes the response control signal B from false to true, and notifies the sending device of the fact that it has been taken in. Upon receiving the response control signal B, the sending device changes the sending of the aforementioned control signal A from true to false. As a result, the device on the receiving side changes the aforementioned control signal B from true to false, and the bus transfer ends.

Now, the first CP connected to the first common input/output bus 3
When the interrupt request input/output instruction from U2 to the second CPU 4 is executed, the address bus 1 on the first common input/output bus 3
In 07, the address of the coupling device is set as the destination device address.
Further, code data indicating an interrupt request to the partner central processing unit is displayed on the data bus 106, and output data transfer is output from the first CPU 2 with the command signal 104 indicating that it is an output command. In the A unit 6 of the coupling device 1, the transfer control circuit 9 detects a change in the address and data transmission control signal 103 from false to true (see FIG. 5).
Bus transfer capture timing signal 1 to allow for hard circuit delays to determine destination device address on address bus
)2 is output. The bus transfer capture circuit 14 uses this timing signal 1) 2 to determine whether the destination device address on the address bus is addressed to itself, and if it is addressed to itself, captures the bus transfer and decodes the command. for I1
0 instruction decoding timing signal 1)8 is output. Opponent c
In the pU interrupt request determination circuit 15, this timing signal 1
) 8 is input, the contents of the data bus 106 are decoded, and if it is a code of a partner CPU interrupt request, a partner CPU interrupt request code 214 is output.

In the response waiting storage circuit 17, the partner system CPU interrupt request signal 2
14, it memorizes that it has entered a state of waiting for a response to an interrupt request, and outputs a waiting response display signal 1) 5 to the bus response control circuit 18. While this display signal 1)5 is true, the bus response control circuit 18 inputs a waiting response to the transfer control circuit 9 via the bus response control signal 109 so as to respond to the bus transfer addressed to itself. The transfer control circuit 9 outputs a response control signal 105 to notify the first CPU 2 that the data output transfer based on the executed output command was a waiting response.

Generally, the first CPU that receives a wait response from the destination device
2 performs retry in hardware without software intervention. This exchange continues between the tenth CPU 2 and the coupling device 1 until a response is returned to the interrupt request to the second CPU 4.

On the other hand, the above-mentioned partner system CPU interrupt request signal 214 is also input to the bus right establishment control circuit 19 of the 8th section 7 of the coupling device 1, and the second common input/output bus 5 is used for bus use in order to issue an interrupt request. A right request signal 201 is output.

Bus use 1)! When receiving a notification that the right to use the bus has been obtained by the establishment control signal 202, the transfer control circuit 20 is notified by the bus right to use establishment signal 208. Transfer control circuit 20
transfers the device address of the CPU, which is the destination address, to the address bus from the CPU address register 24, and transfers data for interrupt control to the data bus from the interrupt control word register 22.
The address/data output control signal 21) is output to each address input/output circuit 23 and data input/output circuit 21, and the address bus 207 is outputted from the address bus 207.
and the data bus 206, while displaying on the command signal 204 that the attribute of the bus transfer is an interrupt request, and further outputting the address and data sending control signal 203 to the second common input/output bus 5.

The second CPU 4 determines whether the destination device address on the address bus is addressed to itself, and if it is addressed to itself, takes in the interrupt control word on the data bus, and executes the interrupt control word and the current program. A response indicating whether to approve or reject the interrupt request is output to the second common input/output bus 5 based on the situation. The coupling device l receives the response control signal 20 of the common input/output bus 5.
5, the response from the CPU is approved or rejected.

Upon receiving this response control signal 205, the transfer control circuit 20 outputs an interrupt response control signal 210 to the synchronization circuit 16.

The synchronization circuit 16 receives I1 from the first CPU 2 described above.
Since the execution of the 0 instruction and the response from the second CPU 4 are asynchronous, the wait response display reset signal 1) 6 is output to the response wait storage circuit 17 after synchronizing the timing. Waiting response display signal 1) 5 changes from true to false, and depending on the approval or rejection state indicated by the interrupt response control signal 210, the approval or rejection response display signal 1
) 7 from false to true. The bus response control circuit 18 sends a response indicating approval or rejection of the waiting response according to the state of the response display signal 1) 7 to the response control signal 105 and the first common input when transferring the interrupt request to the next partner central processing unit via the bus. Output bus 3
It is returned to the first CPU 2 via . The first CPU 2 can know whether the interrupt request has been approved or rejected based on the response when the response I10 instruction is executed.

〔Effect of the invention〕

As explained above, the present invention is capable of recognizing whether an interrupt request command has been accepted or rejected at the time of executing an interrupt request command to the partner central processing unit. This has the effect of saving circuitry and software overhead.

In addition, since the coupling device does not have to wait for approval from the partner central processing unit, it has the effect of making it easier to analyze failures caused by hardware and software, such as loss of interrupt requests, rear-end collisions, and errors. .

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing the configuration of an embodiment system of the present invention. 2 and 3 are block configuration diagrams showing the configuration of the coupling device shown in FIG. 1. FIG. FIG. 4 is a sequence diagram showing the operation of the system according to the embodiment of the present invention. FIG. 5 is a time chart showing the operation of the system according to the embodiment of the present invention. FIG. 6 is a block configuration diagram showing the configuration of a conventional system. 7 and 8 are block configuration diagrams showing the configuration of the coupling device shown in FIG. 6. FIG. FIG. 9 is a time chart showing the operation of the conventional method. 1.1'...Coupling device, 2.4...CPU, 3.5
...Common input/output bus, 8.19...Bus usage right establishment control circuit, 9.20...Transfer control circuit, 10.21.
...Data input/output circuit, 1). 22...Interrupt control'a word register, 12.23...Address input/output circuit, 13
．． 24...CPU address register, 14.25...
- Bus transfer capture circuit, 15.26... Other side CPU interrupt request determination circuit, 16.27... Synchronization circuit, 17.
28...Response waiting storage circuit, 18.29...Bus response side i1) circuit, 30.31...Interrupt re-request circuit, 10
1.201... Bus usage right request signal, 102.202
...Bus use 1)! Establishment control signal, 103.203・
...Address and data transmission control signal, 104.20
4... Command signal, 105.205... Response control signal, 106.206... Data bus signal, 107.
20? ...address bus (l, 108.208...
Bus usage right establishment signal, 109.209... Bus response control signal, 1) 0.210... Interrupt response control signal, 1)
1.21) Address/data output control signal, 1)
2.212...Bus transfer capture timing signal, 1) 4
．． 214...Partner system CPU interrupt request signal, 1) 5.2
15... Wait response display signal, 1) 6.216... Wait response display reset signal, 1) 7.217... Approval or rejection response display signal, 1) 8.218... I10 command decoding timing signal.

Claims (1)

[Claims] (1) An input/output bus to which one central processing unit is connected,
The other central processing unit is interposed in the path between the connected input/output bus, and the one central processing unit receives a response of approval or rejection from the other central processing unit to an interrupt request from the one central processing unit. In a bus coupling device equipped with a notification means for notifying a processing unit, one central processing unit is in this state for a period of time during which it waits for a response from the other central processing unit regarding an interrupt request from the one central processing unit. means (17, 18) for repeatedly sending out a signal indicating the above, and when the other central processing unit responds with approval or rejection, the timing of this response coincides with the timing of the interrupt request from the one central processing unit. means (16, 18) for sending an approval or rejection response from the other central processing unit to the one central processing unit based on the synchronized interrupt request; A bus coupling device characterized by comprising: