JPS63941B2 - - Google Patents
Info
- Publication number
- JPS63941B2 JPS63941B2 JP54109904A JP10990479A JPS63941B2 JP S63941 B2 JPS63941 B2 JP S63941B2 JP 54109904 A JP54109904 A JP 54109904A JP 10990479 A JP10990479 A JP 10990479A JP S63941 B2 JPS63941 B2 JP S63941B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon dioxide
- dioxide layer
- semiconductor substrate
- nitrided
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 31
- 239000004065 semiconductor Substances 0.000 claims description 21
- 235000012239 silicon dioxide Nutrition 0.000 claims description 15
- 239000000377 silicon dioxide Substances 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 9
- 150000002500 ions Chemical class 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 150000004767 nitrides Chemical class 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 5
- 125000004433 nitrogen atom Chemical group N* 0.000 claims 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 16
- 238000005468 ion implantation Methods 0.000 description 12
- 230000015556 catabolic process Effects 0.000 description 9
- 239000004020 conductor Substances 0.000 description 7
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000005121 nitriding Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 230000015654 memory Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical class [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
Landscapes
- Physics & Mathematics (AREA)
- High Energy & Nuclear Physics (AREA)
- Engineering & Computer Science (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造にイオン注入法を利
用する場合、イオン照射を受ける絶縁膜の絶縁破
壊を改善する方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for improving dielectric breakdown of an insulating film subjected to ion irradiation when ion implantation is used in the manufacture of semiconductor devices.
半導体装置の製造にイオン注入を利用すること
は近年盛んに行なわれている。とくに、MOSIC
の製造に於いては、ゲート電極をマスクとしてソ
ース、ドレインを形成する場合、或は、閾値電圧
の調整の為にチヤンネル領域にドープする場合な
どに該法の特長、すなわち不純物の分布する深さ
や濃度が自由に制御できること、横方向の拡がり
が少いことなどの故に多用されている。 In recent years, ion implantation has been widely used in the manufacture of semiconductor devices. In particular, MOSIC
In manufacturing, when forming a source and drain using the gate electrode as a mask, or when doping a channel region to adjust the threshold voltage, the features of this method, such as the depth of impurity distribution and It is widely used because its concentration can be freely controlled and its lateral spread is small.
このような場合、通常半導体ウエフアーの表面
には部分的にイオン注入を妨げる為の遮蔽層が設
けられており、更にイオン注入を行なうべき部分
も薄い絶縁膜で覆われている場合がある。 In such cases, the surface of the semiconductor wafer is usually partially provided with a shielding layer to prevent ion implantation, and the area where ion implantation is to be performed may also be covered with a thin insulating film.
前記遮蔽層としてはフオトレジストや二酸化硅
素(SiO2)、窒化硅素(Si3N4)などが主に用い
られるが、かかる絶縁物をイオンで照射した場
合、その表面に電荷が蓄積されるので、その厚さ
が小である場合には絶縁破壊に対する配慮が必要
である。 As the shielding layer, photoresist, silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), etc. are mainly used, but when such an insulator is irradiated with ions, charges are accumulated on its surface. , when the thickness is small, consideration must be given to dielectric breakdown.
とくに、MOSトランジスタのゲート絶縁膜を
通じてチヤネル領域にイオン注入を行なう場合、
該ゲート絶縁膜は1000Å以下の薄いものである
為、電荷の蓄積による絶縁破壊が生じ易い。更
に、多結晶シリコン層(以下ポリSi層と記す)を
ゲート電極として形成し、これをマスクとしてイ
オン注入を行なう場合、該ポリSi層は配線層形成
までは電気的にフローテイングであることが多
く、ここに多量の電荷が蓄積されることになる。
これは不揮発メモリとして使用されるフローテイ
ングゲート型の構造に於ても同様であり、リーク
電流が集中しやすい状況を考えれば、より苛酷な
条件に置かれていると見るべきである。 In particular, when implanting ions into the channel region through the gate insulating film of a MOS transistor,
Since the gate insulating film is thin with a thickness of 1000 Å or less, dielectric breakdown is likely to occur due to charge accumulation. Furthermore, when a polycrystalline silicon layer (hereinafter referred to as poly-Si layer) is formed as a gate electrode and ion implantation is performed using this as a mask, the poly-Si layer may be electrically floating until the wiring layer is formed. Therefore, a large amount of charge will be accumulated here.
This also applies to floating gate structures used as non-volatile memories, and considering the situation in which leakage current tends to concentrate, it should be seen that the conditions are even more severe.
かかる電荷の蓄積が最近に至つて大きな問題と
みなされるようになつたのは、イオン注入電流の
増大に起因している。 The reason why such charge accumulation has recently come to be considered a major problem is due to the increase in ion implantation current.
即ち、従来のように1mA以下のイオン電流で
あればSiO2等の絶縁膜に蓄積された電荷は、注
入によつて活性化された表面を流れたり、或は永
久破壊を起さない程度の電流値で絶縁膜を通つて
基板に流れることによつて放電される為、特に問
題となることはなかつた。 In other words, if the ion current is 1 mA or less as in the conventional case, the charge accumulated in the insulating film such as SiO 2 will not flow on the surface activated by the injection, or it will flow at a level that does not cause permanent destruction. This did not pose any particular problem because the current was discharged by flowing through the insulating film to the substrate.
しかしながら、近年使用されるシリコンウエア
ーが大型化し、イオン注入の速度も高速化が要求
されるようになり、イオン電流値も大きくなるに
伴つて、何らかの手段によつて放電を助長してや
ることが必要となつてきた。 However, as the size of silicon ware used in recent years has increased, the speed of ion implantation has also increased, and as the ion current value has also increased, it has become necessary to promote discharge by some means. I'm getting old.
以上の状況に鑑み、本発明は本件発明者等が得
た新しい知見に基く電荷放電法を提案するもので
ある。 In view of the above circumstances, the present invention proposes a charge discharge method based on new knowledge obtained by the inventors of the present invention.
本発明者等は、SiO2膜を窒素を含む分子構造
を持つガス中で加熱処理し、その表面をシリコン
窒化物に変換してやれば、永久破壊に至ることな
く流し得るリーク電流値が大幅に増加することを
見出した。 The inventors have found that by heat-treating a SiO 2 film in a gas with a molecular structure containing nitrogen to convert its surface into silicon nitride, the leakage current that can flow without permanent destruction can be significantly increased. I found out what to do.
第1図及び第2図はこの現象及びそれを利用す
る第1の実施例を説明するものである。 FIGS. 1 and 2 explain this phenomenon and a first embodiment that utilizes it.
第1図aに示すような、その表面に500Åの
SiO2膜2が形成された半導体基板1を、アンモ
ニア(NH3)を含む気体中で、1000℃の熱処理
を行ない、SiO2膜の一部を窒化物層3に変換し、
第1図bに示す状態のものを得た。 500 Å on its surface, as shown in Figure 1a.
The semiconductor substrate 1 on which the SiO 2 film 2 is formed is subjected to heat treatment at 1000° C. in a gas containing ammonia (NH 3 ) to convert a part of the SiO 2 film into a nitride layer 3,
A product in the state shown in FIG. 1b was obtained.
該窒化処理を施こした絶縁膜上に直径400μmの
電極を付けMOSダイオードを形成した後、第1
図cのようにそのリーク電流を測定した結果が第
2図に示されている。 After forming a MOS diode by attaching an electrode with a diameter of 400 μm on the nitrided insulating film, the first
The results of measuring the leakage current as shown in Figure c are shown in Figure 2.
第2図に於て、上記の如き窒化処理が行なわれ
た時間が横軸にとられてあり、処理時間Oはこの
ような熱処理を受けなかつたことを意味する。縦
軸は永久的な絶縁破壊を生じたリーク電流値であ
る。図より明らかな如く、1000℃で2時間以上の
窒化処理を施こした場合、かかる処理を全く施こ
さなかつたものに比べて絶縁破壊を起すことなく
2桁近く大きな電流を流すことが可能である。 In FIG. 2, the time during which the above-described nitriding treatment was performed is plotted on the horizontal axis, and the treatment time O means that such heat treatment was not performed. The vertical axis is the leakage current value that caused permanent dielectric breakdown. As is clear from the figure, when nitriding treatment is performed at 1000℃ for 2 hours or more, it is possible to flow nearly two orders of magnitude larger current without causing dielectric breakdown than when no such treatment is performed at all. be.
即ち、イオン注入に於ても、このような処理を
受けたSiO2膜は、受けない場合に比べて2桁近
く大きい速度で電荷を放出し得るので、それに応
じて大電流のイオン注入を可能にする。 In other words, even during ion implantation, a SiO 2 film that has undergone this type of treatment can release charge at a rate nearly two orders of magnitude faster than one that is not subjected to such treatment, making it possible to perform ion implantation with a correspondingly large current. Make it.
シリコン酸化膜の窒化処理法としては、特開昭
50―147877号公報に記されているような方法、即
ちアンモニア或はヒドラジン(N2H4)を含む雰
囲気中で加熱処理する方法が利用可能であり、更
に窒素を含むプラズマに被曝させても、表面を窒
化することができる。 As a nitriding method for silicon oxide film,
A method such as that described in Publication No. 50-147877, that is, a method of heat treatment in an atmosphere containing ammonia or hydrazine (N 2 H 4 ), can be used. , the surface can be nitrided.
前記特開昭50―147877号公報にはSiO2層上に
Si3N4層を形成する技術が開示されているが、
Si3N4層を形成した後イオン注入を施こすことの
記述は全く無く、その可能性を暗示してもいな
い。 In the above-mentioned Japanese Patent Application Laid -open No. 147877,
Although a technique for forming a Si 3 N 4 layer has been disclosed,
There is no mention of performing ion implantation after forming the Si 3 N 4 layer, nor does it hint at the possibility.
更に、前記公報に記載された発明がMNOS型
不揮発メモリに関するものであつて、電荷を蓄え
る為の装置を対象とするのに反し、本発明は電荷
を放出することを目的としている点で両者には大
きな差異のあることを留意すべきである。 Furthermore, while the invention described in the above-mentioned publication relates to a MNOS type nonvolatile memory and is aimed at a device for storing electric charge, the present invention is different from both in that its purpose is to discharge electric charge. It should be noted that there is a large difference between
本発明の第2及び第3の実施例を次に説明す
る。第3図aに示すような構造の場合には、即ち
半導体基板1上にSiO2膜2があり、更にSiO2膜
上に部分的に金属又はポリSiである導電体層5が
形成されている場合にイオン注入を行なうと、導
電体層に注入された電荷は該導電体層5内を自由
に移動し得る為SiO2膜の最も薄い部分に電界集
中を起し、永久的な絶縁破壊が生じ易い。 Second and third embodiments of the invention will now be described. In the case of the structure shown in FIG. 3a, there is a SiO 2 film 2 on a semiconductor substrate 1, and a conductor layer 5 made of metal or poly-Si is partially formed on the SiO 2 film. If ion implantation is performed when the SiO 2 film is ion-implanted, the charges injected into the conductor layer can move freely within the conductor layer 5, causing electric field concentration at the thinnest part of the SiO 2 film, resulting in permanent dielectric breakdown. is likely to occur.
このような場合にも第3図bに示すように、
SiO2膜2の表面に窒化物層3を形成し、その上
に導体層5を形成すれば、絶縁破壊耐量が向上す
る。 Even in such a case, as shown in Figure 3b,
By forming the nitride layer 3 on the surface of the SiO 2 film 2 and forming the conductor layer 5 thereon, the dielectric breakdown strength is improved.
更に、第4図aに示すような構造の場合、即ち
半導体基板1上にSiO2膜2があり、その上に部
分的に導電体層5が形成されており、該導電体層
はSiO2層6によつて覆われている場合には、蓄
積された電荷が活性化されたSiO2層6の表面を
伝わつて逃げることができないので、第3図の場
合以上に絶縁破壊が生じやすい。 Furthermore, in the case of the structure shown in FIG. 4a, that is, there is a SiO 2 film 2 on a semiconductor substrate 1, and a conductor layer 5 is partially formed on it, the conductor layer is made of SiO 2 When covered by layer 6, dielectric breakdown is more likely to occur than in the case of FIG. 3, since the accumulated charges cannot escape through the surface of activated SiO 2 layer 6.
このような場合にも、第4図bに示すように
SiO2層2の上部に窒化物層3を形成することに
よつて破壊耐量が向上する。 In such a case, as shown in Figure 4b,
By forming the nitride layer 3 on top of the SiO 2 layer 2, the breakdown strength is improved.
以上述べたように本発明によれば、部分的に或
は全面的に酸化物層で覆われた半導体基板に大電
流のイオン注入を施すことが可能となる。 As described above, according to the present invention, it is possible to perform ion implantation with a large current into a semiconductor substrate partially or completely covered with an oxide layer.
第1図〜第4図は本発明を説明する図であつて
1は半導体基板、2,6はSiO2層、3は窒化シ
リコン層、4はAl電極、5は導電体層である。
1 to 4 are diagrams for explaining the present invention, in which 1 is a semiconductor substrate, 2 and 6 are SiO 2 layers, 3 is a silicon nitride layer, 4 is an Al electrode, and 5 is a conductor layer.
Claims (1)
基板を窒素原子を含む雰囲気中において熱処理し
て前記二酸化シリコン層の表面を窒化し、しかる
後前記表面が窒化された二酸化シリコン層を通し
て前記半導体基板中にイオン注入を行う工程を有
することを特徴とする半導体装置の製造方法。 2 表面に二酸化シリコン層が形成された半導体
基板を窒素原子を含む雰囲気中において熱処理し
て前記二酸化シリコン層の表面を窒化し、次いで
前記表面が窒化された二酸化シリコン層上に選択
的に導電層を形成し、しかる後前記表面が窒化さ
れた二酸化シリコン層を通して前記半導体基板中
にイオン注入を行う工程を有することを特徴とす
る特許請求のの範囲第1項記載の半導体装置の製
造方法。 3 表面に二酸化シリコン層が形成された半導体
基板を窒素原子を含む雰囲気中において熱処理し
て前記二酸化シリコン層の表面を窒化し、次いで
前記表面が窒化された二酸化シリコン層上に選択
的に導電層を形成し、次いで前記導電層を被覆す
る絶縁層を形成し、しかる後前記表面が窒化され
た二酸化シリコン層を通して前記半導体基板中に
イオン注入を行う工程を有することを特徴とする
特許請求の範囲第1項記載の半導体装置の製造方
法。 4 表面に二酸化シリコン層が形成された半導体
基板に対して窒素原子を含む雰囲気中において行
われる熱処理は、前記表面に二酸化シリコン層が
形成された半導体基板を励起された窒素原子を含
むプラズマ雰囲気に晒すことにより行われること
を特徴とする特許請求の範囲第1項記載の半導体
装置の製造方法。[Scope of Claims] 1. A semiconductor substrate having a silicon dioxide layer formed on its surface is heat-treated in an atmosphere containing nitrogen atoms to nitride the surface of the silicon dioxide layer, and then a silicon dioxide layer with the surface nitrided. A method of manufacturing a semiconductor device, comprising the step of implanting ions into the semiconductor substrate through the semiconductor substrate. 2. A semiconductor substrate with a silicon dioxide layer formed on its surface is heat-treated in an atmosphere containing nitrogen atoms to nitride the surface of the silicon dioxide layer, and then a conductive layer is selectively formed on the silicon dioxide layer whose surface has been nitrided. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of forming a silicon dioxide layer having a nitrided surface and then implanting ions into the semiconductor substrate through the silicon dioxide layer whose surface is nitrided. 3. A semiconductor substrate with a silicon dioxide layer formed on its surface is heat-treated in an atmosphere containing nitrogen atoms to nitride the surface of the silicon dioxide layer, and then a conductive layer is selectively formed on the silicon dioxide layer whose surface has been nitrided. and then forming an insulating layer covering the conductive layer, and then implanting ions into the semiconductor substrate through the surface-nitrided silicon dioxide layer. 2. A method for manufacturing a semiconductor device according to item 1. 4 Heat treatment performed on a semiconductor substrate with a silicon dioxide layer formed on the surface in an atmosphere containing nitrogen atoms is performed by heating the semiconductor substrate with a silicon dioxide layer formed on the surface in a plasma atmosphere containing excited nitrogen atoms. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the method is carried out by exposing.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10990479A JPS5633819A (en) | 1979-08-29 | 1979-08-29 | Preparation of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10990479A JPS5633819A (en) | 1979-08-29 | 1979-08-29 | Preparation of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5633819A JPS5633819A (en) | 1981-04-04 |
JPS63941B2 true JPS63941B2 (en) | 1988-01-09 |
Family
ID=14522096
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10990479A Granted JPS5633819A (en) | 1979-08-29 | 1979-08-29 | Preparation of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5633819A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50147877A (en) * | 1974-05-08 | 1975-11-27 |
-
1979
- 1979-08-29 JP JP10990479A patent/JPS5633819A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50147877A (en) * | 1974-05-08 | 1975-11-27 |
Also Published As
Publication number | Publication date |
---|---|
JPS5633819A (en) | 1981-04-04 |
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