JPS639314A - Bit synchronization type timing circuit - Google Patents

Abstract

PURPOSE:To quicken data demodulation by constituting the titled circuit by an oscillator, plural delay lines. e multiplexer connected to the delay lines, a decoder controlling the multiplexer and a gate circuit extracting a signal pulse and generating a synchronizing signal from the output of the oscillator through the delay lines. CONSTITUTION:In inputting a start bit to a DATA input, an R-S flipflop 6 is set and an output of the delay line synchronously with the start bit is set in the data latch 9. Then the output is supplied to a decoder 5, where the signal is decoded as a binary data 101 and the result is fed to a multiplexer 3. A pulse optimum for data demodulation is fed to a selector terminal among a series of timing pulses retarded via the delay line. Thus, the output timing pulse from the multiplexer 3 is outputted and counted by a counter 2. A signal having a period being a multiple of two to the n-th power is outputted at a proper output terminal Qn of the counter 2. Then the titled circuit is operated at a low frequency as 1/8-1/16.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a bit-synchronized demodulation circuit, and particularly to a bit-synchronized timing circuit that utilizes a delay line.

[Technical Background of the Invention] As shown in FIG. 2, conventionally, in order to obtain the necessary synchronization signal in a bit-synchronized demodulation circuit, an oscillator has been used to generate a signal with a frequency of 8 to 16 times that of the synchronization signal. , which was obtained by dividing the frequency using a counter or the like and decoding it.

[Problems with Background Art] However, conventional timing circuits have had problems such as demodulation being sometimes impossible due to the response frequency limit of the elements used for frequency division.

[Object of the invention] The present invention has been made to solve the above-mentioned inconvenience.
The present invention aims to provide a bit-synchronized timing circuit capable of high-speed data demodulation by creating the 111111ir signal from the output of an oscillator using a delay line.

[Summary of the Invention] In order to achieve the above object, a bit synchronous timing circuit according to the present invention includes an oscillator, a plurality of delay lines connected to the output of the oscillator, and a multiplexer connected to the delay lines. , a decoder that receives the output of the delay line and controls the multiplexer, and a gate circuit that extracts signal pulses from the output of the multiplexer.

[Embodiments of the Invention] Preferred embodiments of the present invention will be described below with reference to FIG. This embodiment is composed of an oscillator 7, a delay line 8, a multiplexer 3, a decoder 5, a D flip-flop 1 as a gate circuit, a counter 2, an AND 4, and an R-S flip-flop 6. The connection relationship is that the oscillator 7 is connected to the delay line 8, the delay line 8 is connected to the multiplexer 3 and the data latch 9, the data latch 9 is connected to the decoder 5, the decoder 5 is connected to the multiplexer 3, the multiplexer 3 is connected to the counter 2, The counter 2 is connected to the AND4 and the RS flip-flop 6, the counter 2 is connected to the RS flip-flop 6, and the RS flip-flop 6 is connected to the data latch 9 and the AND4, respectively. Human power 1 word a is D flip-flop 1
, R-S flip-flop 6 at the same time.

Next, the operation of the circuit of this embodiment will be explained.The zero oscillator 7 generates pulses at a constant frequency approximately equal to the frequency of human input data. The pulses are passed through multiple delay lines, and the outputs are signals that are slightly out of phase. The timings of these signals are shown, for example, in FIG. 3 from QO to Q5. Signals with higher numbers have a delayed phase. Assume that the RS flip-flop 6 has been reset. Now, when a start bit is manually input to DATA, the R-S flip-flop 6 is set, and the output of the delay line synchronized with the start bit is set to the data latch 9.

The latch signal shown in FIG. 3C remains in the ON state until it is reset thereafter. Its set value is given to multiplexer-3. Among the series of timing pulses delayed through the delay line, the pulse d (Q5 in this case) most suitable for data demodulation is repeatedly supplied to the multiplexer 3 to one terminal of the selector. The multiplexer 3 output timing pulse is thus output and counted by the counter 2. An appropriate output terminal Qn of the counter 2 outputs a signal with a period that is a power of 2, and this output resets the R-S flip-flop 6, and the latch 9 receives data again. On the other hand, the input from the multi-plexer 3 output ζ is applied to the flip-flop l.

Since the front end of the pulse transmits the value of 0 human power to the Q output and holds it there, data is extracted by the human power timing pulse. In this way, the human data is adjusted for one summer, and the data is extracted.

If you read M1 table 6, decoder manual binary '10000111'
In this case, the decoder output (manual power of multiplexer) is 2 ways '101', and the output of multiplexer 3 is Q6.

[Effects of the Invention] As can be seen from the above embodiments, the bit-synchronized timing circuit of the present invention obtains a synchronizing signal from the output of the oscillator through a delay line. Therefore, the fundamental frequency may be approximately the same as the data transmission rate, and it is possible to operate at a lower frequency of about 1/8 to 1/16 compared to the conventional method of synchronizing using a counter or the like. In other words, faster data demodulation is possible using the same number of circuit elements.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a bit synchronized timing circuit according to the present invention, and FIG. 2 is a block diagram showing an embodiment of a bit synchronized timing circuit according to the present invention.
The third example is a block diagram showing an embodiment of the bit-synchronized timing circuit according to the present invention. 1, , D flip-flop (gate circuit) 210. Counter (gate circuit) 38. , multiplexer 4, , AND (gate circuit) 511. Decoder 6,..., R-S flip-flop (gate circuit) 706
4 oscillator 891. Delay line 961. latch ward

Claims (1)

[Claims] an oscillator, a plurality of delay lines connected to the output of the oscillator, a multiplexer connected to the delay line, a decoder receiving the output of the delay line and controlling the multiplexer, and an output of the multiplexer. A bit synchronized timing circuit comprising a gate circuit for extracting signal pulses from a gate circuit.