JPH0310428A - Frame aligner device - Google Patents

Abstract

PURPOSE:To prevent a burst error due to jitter-wander with simple constitution by varying a phase sent from an opposite device in a frame aligner means of a synchronizing multiplexer. CONSTITUTION:Two devices placed opposite to each other apply data transmission via transmission lines 130, 141. Frame synchronization is taken by receiving a signal from the transmission line 13, the phase of a write reset signal 134 and that of a readout reset signal 135 are compared with each other and a delay obtaining an optimum phase is sent to an opposite device via the transmission line 130 as a sub data signal. The opposite device receives the data to change the phase of the readout reset signal 123 at a pulse generating circuit 102 thereby applying data transmission with an optimum phase at all times. Thus, the production of a burst error due to jitter-wonder or the like is prevented with simple constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is applied to a synchronous multiplexing device. In particular, it relates to frame aligner circuits.

〔overview〕

The present invention makes it possible to prevent burst errors due to jitter wander with a simple configuration by changing the sending phase of opposing devices led by frame aligner means of a synchronous multiplexer.

[Conventional technology]

In the conventional example, as shown in FIG.
a clock oscillation circuit 201 that outputs 0, a pulse generation circuit 202 that outputs a read reset signal 221 and a pulse signal 222 in response to a transmission clock signal 220, a write data signal 223, and a write reset signal 2.
24, an elastic store 203 which inputs a write clock signal 225, a transmission clock signal 220 and a read reset signal 221; and a transmission data signal 227 which inputs a read data signal 226 and a transmission clock signal 220 output from the elastic store 203;
a frame insertion circuit 204 that outputs a data signal 22;
7 and the transmission clock signal 220 manually, and the transmission line 22
8 and a transmission line 228.
a decoding circuit 206 that receives data from the computer and outputs a received data signal 229 and a received clock signal 230; and a decoding circuit 206 that manually receives data from the received data signal 229 and received clock signal 230, performs frame synchronization, and outputs a data signal 231 and a frame signal 232. frame synchronization circuit 207
Then, the data signal 231, the frame signal 232, and the received clock signal 230 are manually input, and the delay circuit 208 which applies a delay and outputs the delayed data signal 233 and the delayed frame signal 234, and the data signal 231 and the frame signal 232 are selected. Alternatively, a selection circuit 209 that determines whether to select the delayed data signal 233 and the delayed frame signal 234, the selection data signal 235 and selection frame signal 236 which are outputs of the selection circuit 209, the reception clock signal 230, and the read reset signal 237. ,
The elastic store 211 uses the read clock signal 238 manually and outputs the read data signal 235.
and a phase comparison circuit 210 that compares the phases of the selected frame signal 236 and the read reset signal 237 and outputs a selection signal 240 that selects the correct data signal and frame signal.

In this conventional example, the pulse generating circuit 202 on the data transmitting side free-runs, without specifying the phase of the data sent to the transmission path 228, and after establishing frame synchronization on the receiving side, the data signal and frame signal are and create two phases by adding a delay to the read reset signal 237.
The phase is compared with the selected frame signal 236, and the elastic store 211 performs speed conversion and matches the phase without error.

[Problem that the invention seeks to solve]

In such a conventional example, it is necessary to provide two phases for the data signal and the frame signal on the receiving side, and there is a drawback that a delay circuit using a shift register with an extremely long delay time is required. In addition, when the received signal from the transmission path shifts in phase due to jitter wander during data transmission and reaches a phase that causes an error during speed conversion, the selection circuit switches between the data signal and frame signal, and burst It has the disadvantage of causing errors.

The present invention aims to eliminate such drawbacks and provides a frame aligner device that can prevent burst errors due to jitter wander and the like.

[Means for solving problems]

The present invention is connected to a first elastic store and a device having a pulse oscillation circuit that provides a read reset signal to this elastic store, and a second elastic store that is connected to a device that includes a pulse oscillation circuit that provides a read reset signal to this elastic store. A phase comparison circuit that compares the phase with the first order of the read reset signal to obtain a phase difference, and a delay time related to the write data signal given to the second elastic store according to the phase difference obtained by this phase comparison circuit. In the frame aligner device, the delay time setting means includes a latch circuit that holds for a predetermined period a signal indicating a phase difference obtained by the phase comparison circuit, and a signal held by the latch circuit. circuit means for supplying a signal indicative of a phase difference to the pulse oscillation circuit; It is characterized by having a means for changing.

[Effect]

The phase of the read reset signal and the write reset signal of the elastic memory within the own device are compared, and the amount of delay to bring the phase to the optimum phase is transmitted to the opposing device. In the opposing device, the transmitted data is manually applied to a pulse generation circuit that provides a read reset signal to the elastic memory in the device, and the phase of this read reset signal is changed.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, this embodiment uses a clock oscillation circuit 101 that sends out a transmission clock signal 121, a transmission clock signal 121 and a sub-data signal 122, and a first read reset signal 123 and a pulse signal 124. and an elastic store 103 that manually generates a write data signal 125, a write reset signal 126, a write clock signal 127, a transmission clock signal 121, and a read reset signal 123, and outputs a read data signal 128.
, read data signal 128, and transmit clock signal 12
1 and the pulse signal 124 manually and outputs the first transmission data signal 129; and a code circuit 105 that uses the transmission data signal 129 and the transmission clock signal 121 manually and outputs the data signal to the transmission path 130. , the data signal from the transmission line 130 is human-powered,
A decoding circuit 106 that outputs a received data signal 131 and a received clock signal 132; a frame synchronization circuit 107 that receives the received data signal 131 and the received clock signal 132 and outputs a write data signal 133 and a write reset signal 134; signal 13
3. Write reset signal 134, receive clock signal 1
32, the read reset signal 135 and the read clock signal 136 are manually operated, and the read data signal 144 is
an elastic store 108 that outputs a write reset signal 134 and a read reset signal 135 manually, and a phase comparator circuit 11 that outputs a delayed signal 137.
) 9, a latch circuit 110 that receives the delayed signal 137 and sends out a sub data signal, a sub data signal 138, a second
The encoder circuit 111 inputs the data signal 139 and the second clock signal 140 and outputs data to the transmission line 141, and inputs the data signal from the transmission line 141.
3 and a decoding circuit 112 that outputs a second sub data signal 122. That is, in this embodiment, elastic store 103 and elastic store 1
Pulse oscillation circuit 1 that gives a read reset signal to 03
Elastic Store 1
08, a phase comparison circuit 109 that compares the phase of the write reset signal applied to the elastic store 108 with the phase of the read cent signal to obtain a phase difference; The present invention is further equipped with a delay time setting means for setting a delay time related to the write data signal applied to the stick store 103, and further, as a feature of the present invention, the delay time setting means is configured to calculate the phase difference obtained by the phase comparator circuit 109. A latch circuit ll that holds a signal indicating for a predetermined period of time
The pulse oscillation circuit 102 includes an encoding circuit 111 and a decoding circuit 112, which are circuit means for providing a signal indicating the phase difference held by the latch circuit 110 to the pulse oscillation circuit 102. The device includes means for changing the phase of a read reset signal generated by its own circuit in response to a signal indicating .

Next, the operation of this embodiment will be explained. Two devices face each other and perform data transmission via transmission path 130 and transmission path 141. The signal from the transmission line 130 is received and frame synchronized, and the phase difference between the write reset signal 134 and the read reset signal 135 is measured, and the phase is determined so that the elastic store 108 can perform clock switching most safely and without error. The delay amount is latched by the latch circuit 110, and the code circuit 111 determines, for example, that the code of the transmission path is CM!
In the case of a code, it is sent to the opposing device using CRV. The decoding circuit 112 that received this signal extracts the delay amount signal and sends this information to the pulse generation circuit 102,
The read reset signal 123 is changed to control the output of the data signal to be sent to the optimum phase.

That is, the phases of the write reset signal 134 and the read reset signal 135 are compared, and the delay amount for achieving the optimum phase is transmitted as a sub data signal to the opposing device via the transmission line 130. The opposing device receives this data and changes the phase of the read reset signal 123 using the pulse generating circuit 102, thereby always transmitting data at the optimum phase.

〔Effect of the invention〕

As explained above, the present invention changes the sending phase of the opposing device by sending data with a delay amount that provides the optimal phase difference to the opposing device using the sub data signal, so frame alignment is always performed at the optimal phase. It has the effect of making it possible. Furthermore, it eliminates the need for a delay circuit for delay insertion/removal, and has the effect of simplifying the configuration compared to the conventional example. Furthermore, since delay insertion/removal is executed when jitter wander occurs during data transmission, data errors due to bursts can be eliminated.

lot, 201...clock oscillation circuit, 102.2
02...Pulse generation circuit, 103.108.203.
21!・・・Elastic Store, 104.204・
...Frame insertion circuit, 105.111, 205...
・Encoding circuit, 106.112.206... decoding circuit,
107.20? ...Frame synchronization circuit, 109.21
0... Phase comparison circuit, 110... Latch circuit, 13
0.141...Transmission line, 208...Delay circuit, 20
9...Selection circuit.

Claims (1)

[Claims] 1. Connected to a first elastic store and a device equipped with a pulse oscillation circuit that provides a read reset signal to this elastic store, and a second elastic store that is provided to this elastic store. A phase comparison circuit that compares the phase of the write reset signal and the phase of the read reset signal to obtain a phase difference; and a write data signal that is applied to the second elastic store according to the phase difference obtained by this phase comparison circuit. In a frame aligner device equipped with a delay time setting means for setting the related delay time, the delay time setting means includes a latch circuit that holds a signal indicating a phase difference obtained by the phase comparison circuit for a predetermined time, and a latch circuit that The pulse oscillation circuit includes circuit means for supplying a signal indicative of the held phase difference to the pulse oscillation circuit, and the pulse oscillation circuit adjusts the phase of a read reset signal generated by the circuit in response to the signal indicative of the phase difference supplied to the circuit. A frame aligner device comprising means for changing the frame aligner.