JPH06291753A - Data transmitter - Google Patents

Abstract

PURPOSE:To prevent faults such as data errors and step-out due to a distance difference between terminal equipments. CONSTITUTION:This transmitter is constituted of a line receiver circuit 1, a timing extraction circuit 2 for extracting clock signals from the output, a frame synchronizing circuit 3 for inputting digital signals and outputting frame synchronizing signals through the clock signals, a multiplexing/demultiplexing circuit 4 for receiving the respective signals and prescribed transmission data and generating transmission data strings for transmission output and reception data strings for internal circuits and a line driver circuit 5 for generating transmission line signals from the transmission data strings. As the clock signals outputted from the timing extraction circuit 2, time control signals proportional to the rising time of the transmission line signals in the line receiver circuit 1 are received and timing-controlled time shift clock signals are generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission device,
In particular, it relates to a synchronous data transmission device used as a terminal device by a point-to-multipoint connection.

[0002]

2. Description of the Related Art A block diagram of an example of a conventional data transmission apparatus of this type is shown in FIG. As shown in FIG. 5A, in this conventional example, a transmission line signal input terminal 89 connected to the reception line of the transmission line, a transmission line signal output terminal 90 connected to the transmission line of the transmission line, and an external A line receiver circuit 51 for inputting a transmission path signal of a transmission path and outputting a digital signal corresponding to a reception data output terminal 91 and a transmission data input terminal 92 connected to the input / output of a data processing device, A timing extraction circuit 52 which inputs the digital signal and outputs a clock signal, a frame synchronization circuit 53 which inputs the digital signal and the clock signal and outputs a frame synchronization signal, and a transmission data which is transmitted. A configuration including a multiplexing / demultiplexing circuit 54 that outputs a data string and received data, and a line driver circuit 55 that inputs the transmission data string and outputs a transmission path signal It is.

In FIG. 5A, a transmission path signal sent via a transmission path, for example, a bipolar code or AMI (Alternative Mark Inversion: AMI, hereinafter).
The code is input to the line receiver circuit 51 and decoded into a digital signal. The signal decoded by the line receiver circuit 51 is output to the timing extraction circuit 52, the frame synchronization circuit 53 and the multiplexing / demultiplexing circuit 54.
Entered in. In the timing extraction circuit 52, a clock synchronized with the decoded digital signal is generated and supplied to the internal logic circuit. In the frame synchronization circuit 53, a specific bit pattern included in the decoded received signal sequence in a constant cycle is detected, and frame synchronization is established. In the multiplexing / demultiplexing circuit 54,
After the frame synchronization is established in the frame synchronization circuit 53, only the data is separated from the received signal sequence and the data is input to the external data processing device. In addition, in the multiplexing / demultiplexing circuit 54, from an external data processing device,
A frame and the like are added to the transmission data transmitted via the transmission data input terminal 92 to form a transmission frame. This transmission frame is encoded from a digital signal to a transmission line signal in the line driver circuit 55 and sent to the transmission line via the transmission line signal output terminal 90. This transmission frame has a timing extraction circuit 52.
In this case, the transmission signal is transmitted in synchronization with the reception signal.

FIG. 5B is a circuit diagram showing an example of the line receiver circuit 51 shown in FIG. 5A. Figure 5
As shown in (b), code input terminals 93 and 9
4, corresponding to the power supply terminal 95 and the output terminal 96, a transformer circuit 56, resistors 57 to 62 and 65, and comparator circuits 63 and 64 are provided. 6 (a), (b), (c) and (d) are similar to FIG.
It is a figure which shows the electric potential level of each part in the line receiver circuit of (b), and shows the input waveform of the code | symbol input terminals 93 and 94, the electric potential level of the node B, the electric potential level of the node C, and the output waveform of the output terminal 96, respectively. ing. Below, FIG.
The operation of the line receiver circuit will be described with reference to (b) and FIG.

The potential of the node A, that is, the comparator circuit 63
The threshold voltages of 64 and 64 are set to V _t (V) exceeding V _cc (V) / 2 by the voltage division ratio of the resistors 61 and 62. When no signal, that is, an AMI signal corresponding to binary "1" is input to the code input terminals 93 and 94 (see FIG. 6A), the node B (FIG. 6B)
(See FIG. 6C) and the potential of the node C (see FIG. 6C) are divided by the resistance resistors 59 and 60, and both are _Vcc (V) /
It becomes 2. Since the threshold voltages of the comparator circuits 63 and 64 are set to V _t (V) as described above, both the comparator circuits 63 and 64 are turned off, and the potential of the output terminal 96 (see FIG. )), V _cc (V), that is, binary "1" is output. Then 2
When a positive pulse corresponding to the base "0" is input,
Since the potential of the node B becomes equal to or higher than the threshold voltage of the comparator circuit 63, the comparator circuit 63 is turned on and 0 (V), that is, binary “0” is output to the output terminal 96.
Is output.

Further, when a negative pulse corresponding to binary "0" is input, the potential of the node C becomes higher than the threshold voltage of the comparator circuit 64, and the comparator circuit 64
Is turned on, and binary "0" is output to the output terminal 96 as in the case where a positive pulse is input.

FIG. 5C is a block diagram showing the configuration of the timing extraction circuit 52 shown in FIG. 5A, which corresponds to the input terminal 97 and the output terminal 98 and the phase comparison circuit 66 and the loop. A filter 67 and a frequency dividing circuit 68 are provided. As is apparent from FIG. 5C, the timing extraction circuit 52 forms a kind of phase synchronization system, and the input signal inputted from the input terminal 97 and the frequency dividing circuit 6 are inputted.
The output signals of 8 are phase-compared in the phase comparison circuit 66, and the phase difference signal is input to the loop filter 67 to reduce jitter and the like and is input to the frequency dividing circuit 68. In the frequency divider circuit 68, the frequency division ratio is controlled and adjusted via the phase comparison information of the previous stage, and the phase of the output signal output from the output terminal 98 is output following the input signal.

[0008]

In the above-mentioned conventional data transmission circuit, in order to extract the clock signal from the received signal, as shown in FIG. 7, two or more terminal devices (in the example of FIG. 7, Is the terminal devices 70-1 and 70
-2) is connected in the point-to-multipoint mode, the terminal device 701 located near the master station 69 and the terminal device 7 located at the far end of the master station 69.
Between 0 and 2, the clock signal extracted in each terminal device has a phase difference proportional to the line distance d between the terminal devices due to the influence of the distributed capacitance of the transmission line and the resistance component. In each of these terminal devices, a transmission signal that is synchronized with the extracted clock is generated and output. Therefore, when the phase difference gradually increases depending on the distance between the terminal devices, the transmission signal output from each terminal device is transmitted. Overlapping signals occur, which increases the data error rate at the master station,
There is a drawback in that it causes a loss of synchronization.

[0009]

A data transmission apparatus of the present invention receives a line signal which receives a transmission path signal, decodes it, and outputs a predetermined digital signal, and an output of the line receiver circuit, A timing extraction circuit for extracting a clock signal from the output and outputting the clock signal;
Input the digital signal included in the output of the receiver circuit,
A frame synchronization circuit that outputs a frame synchronization signal via the clock signal, and a transmission data sequence for transmission output and a reception data sequence for an internal circuit that receives the digital signal, the clock signal, the frame synchronization signal, and predetermined transmission data A demultiplexing / demultiplexing circuit that generates and outputs
A line driver circuit that receives the transmission data string and generates and outputs a transmission line signal is generated in the line receiver circuit as a clock signal output from the timing extraction circuit. In response to a time control signal proportional to the rise time of the transmission line signal, the timing extraction circuit generates and outputs a time shift clock signal whose timing is controlled by the time control signal.

The timing extraction circuit includes a clock signal extracted from the output of the line receiver circuit and a delayed clock signal obtained by delaying the phase of the time shift clock signal output from the timing extraction circuit. Of the loop filter that inputs the phase difference information output from the phase comparator and outputs the high frequency component included in the phase difference information after removing the high frequency component A frequency divider circuit which receives the output and controls and adjusts the frequency division ratio to output the time shift clock signal, and a delay amount which is controlled by a time control signal output from the line receiver circuit. And a delay circuit for generating the delayed clock signal by delaying the phase thereof and outputting the delayed clock signal.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. As shown in FIG. 1, in this embodiment, a transmission line signal input terminal 71 connected to a reception line of a transmission line, a transmission line signal output terminal 72 connected to a transmission line of a transmission line, and an external data processing device. A line receiver circuit which inputs a transmission path signal of a transmission path and outputs a digital signal and a rise time detection signal corresponding to a reception data output terminal 73 and a transmission data input terminal 74 which are connected to inputs and outputs of 1, the digital signal and the rise time detection signal are input,
A timing extraction circuit 2 that outputs a clock signal, a frame synchronization circuit 3 that inputs the digital signal and the clock signal and outputs a frame synchronization signal, and the digital signal, the clock signal, the frame synchronization signal, and the transmission data are input. In addition, the multiplexer / demultiplexer circuit 4 for outputting the transmission data string and the reception data, and the line driver circuit 5 for inputting the transmission data string and outputting the transmission path signal are configured. In addition, FIG.
3 is a circuit diagram of the line receiver circuit 1 and a block diagram of the timing extraction circuit 2 shown in FIG. 1, respectively, and FIG. 3 (a), (b), (c), (d), (e), (f). ,
4 (g) and 4 (h) are operation waveform diagrams of the respective parts in the line receiver circuit 1, and FIG.
(B) and (c) show operation waveform diagrams of each part in the timing extraction circuit 2.

In FIG. 1, a transmission line signal sent via a transmission line is input to a line receiver circuit 1 and decoded into a digital signal, and a rise time detection signal is generated and output. It The digital signal and rise time detection signal output from the line receiver circuit 1 are output to the timing extraction circuit 2 and the frame synchronization circuit 3.
And input to the multiplexing / demultiplexing circuit 4. In the timing extraction circuit 2, a digital signal and a rise time detection signal are input, a clock signal synchronized with these signals is generated and supplied to an internal logic circuit. In the frame synchronization circuit 3, a digital signal and a clock signal are input, a specific bit pattern included in the decoded received signal sequence at a constant cycle is detected, a frame synchronization signal is generated, and multiplexing / demultiplexing is performed. It is input to the circuit 4. A clock signal is also input from the timing extraction circuit 2 to the multiplexing / demultiplexing circuit 4, and the frame synchronization circuit 3
After the frame synchronization is established in, only the data is separated from the received signal sequence and the data is input to the external data processing device. Further, in the multiplexing / demultiplexing circuit 4,
From the external data processing device, the transmission data input terminal 74
A frame and the like are added to the transmission data input via the so-called transmission frame. This transmission frame is encoded in the line driver circuit 5 from a digital signal into a transmission path signal, and sent out to the transmission path via the transmission path signal output terminal 72. This transmission frame is composed of the clock signal generated in the timing extraction circuit 2, and the transmission signal is transmitted in synchronization with the reception signal.

FIG. 2A is a circuit diagram showing an example of the line receiver circuit 1 shown in FIG. As shown in FIG. 2A, the transformer circuit 6 corresponds to the code input terminals 75 and 76, the power supply terminal 77, the output terminal 78, the system check terminal 79 and the control signal output terminal 80.
, Comparator circuits 7, 8, 18 and 19, resistors 9 to 17 and 26, inverter 20, AND circuits 21 and 22, count circuit 23, and latch circuit 2
4 and a decoding circuit 25. The operation waveform diagrams of the respective parts in the line receiver circuit 1 are shown in FIGS. 3 (a), (b), (c), (e) and (f). ,
Shown in (g) and (h). In addition, FIG.
2 is a block diagram showing an example of the timing extraction circuit 2 shown in FIG. 1, in which a phase comparator 27 and a delay circuit 28 are provided corresponding to an input terminal 81, a control signal input terminal 82 and an output terminal 83.
, A loop filter 29, and a frequency dividing circuit 30. 4 (a), (b) and (c)
6 is an operation waveform diagram of each part in the timing extraction circuit 2. FIG.

The operation of this embodiment will be described below with reference to FIGS. 1, 2, 3 and 4.

The potentials at the nodes D and E in the line receiver circuit 1 shown in FIG.
It is assumed that the high threshold voltage V _H (V) and the low threshold voltage V _L (V) are set by the voltage dividing circuits 17 and 17, respectively. These threshold voltages are input to the negative phase side input terminals of the comparator circuits 18 and 19, respectively. Now, when the transmission line signal shown in FIG. 3A is input to the transmission line signal input terminal 71,
As the output 102 of the comparator circuit 18 and the output 101 of the comparator circuit 19 in the line receiver circuit 1 shown in FIG. 2A, the outputs shown in FIGS. 3D and 3C are obtained. The output 102 of the comparator circuit 18 is inverted by the inverter 20 and input to the AND circuit 21. In the AND circuit 21, the output of the inverter 20 and the output 101 of the comparator circuit 19 are ANDed, Its output 103
(See FIG. 3E) is input to the AND circuit 22. A
In the ND circuit 22, the output 1 of the AND circuit 21
03 and the clock signal 104 (see FIG. 3 (f)) input from the system check terminal 79 are ANDed, and the output is input to the counter circuit 23. The counter circuit 23 is an n-bit counter circuit, and AND
The high level at the output of circuit 22 is counted by the system clock signal at a sufficiently high frequency. The output 105 of the counter circuit 23 (see FIG. 3G) is input to the latch circuit 24, but the count value is held at the rising edge of the comparator circuit 18. Further, assuming that the counter circuit 23 is reset at the falling edge of the comparator circuit 19, in the latch circuit 24, as shown in FIG. 3, ΔH ₁ , that is, a value proportional to the rising time of the transmission path signal. Is retained. In the decode circuit 25 connected to the latch circuit 24, the output 106 of the latch circuit 24 is decoded,
It is output via the control signal output terminal 80.

As described above, the line receiver circuit 1
, The rise time ΔH of the received transmission line signal is
It is possible to output a control signal proportional to ₁ , and the control signal is the control signal output terminal 8 in FIG.
It is output from 0 and is connected to the control signal input terminal 82 of the timing extraction circuit 2 shown in FIG. This control signal is supplied to the delay circuit 28 in the timing extraction circuit 2.
It is input to and acts to control and adjust the delay amount. Now, in FIG. 2B, it is assumed that the delay amount of the delay circuit 28 is set to φ ₁ by the control signal input from the line receiver circuit 1. The input signal obtained by decoding the transmission path signal input from the line receiver circuit 1 via the input terminal 81 is compared in phase with the output signal of the delay circuit 28 in the phase comparison circuit 27, and the phase comparison information is looped. The high frequency component is removed by the filter 29 and input to the frequency dividing circuit 30. In the frequency dividing circuit 30, the frequency dividing ratio is controlled and adjusted by the phase comparison information, and a signal synchronized with the received signal is obtained at the output of the delay circuit 18. That is, the timing extraction circuit 2 shown in FIG. 2B operates so that the reception signal input to the phase comparator 27 and the output signal of the delay circuit 28 are synchronized. The input signal to the delay circuit 28, that is, the frequency divider 30
If the output of is output as the clock signal from the output terminal 83, a clock signal whose phase is advanced by φ _{1 with} respect to the received signal can be obtained. Since this phase difference φ ₁ increases in proportion to the rising time of the reception waveform, the terminal device connected to the far end of the main station outputs the transmission signal at an earlier timing than the reception signal. By configuring the data transmission device in this way, the phase difference between the transmission signals sent from two or more terminal devices is compressed, and the data error rate in the main station due to the distance difference between the terminal devices is included. The obstacle is resolved.

Next, a second embodiment of the present invention will be described.

FIG. 5 is a circuit diagram showing another example of the line receiver circuit 1 shown in FIG. 1 in this embodiment.
As shown in FIG. 5, the line receiver circuit is
Corresponding to the sign input terminals 84 and 85, the power supply terminal 86, the output terminal 87, the system clock input terminal 88 and the control signal output terminal 89, the transformer circuit 31, the comparator circuits 32, 33, 43 and 44, and the resistor 34. ~
42 and 50, an inverter 45, and an AND circuit 46
And a 2 ^n- bit shift register 47 and a latch circuit 4
8 and a code conversion circuit 49. Figure 5
In the above, the main difference between the line receiver circuit and the line receiver circuit in the first embodiment is 2
The circuit configuration includes an ^n- bit shift register 47, a latch circuit 48, a code conversion circuit 49, and the like.

The output of the comparator circuit 43 is inverted by the inverter 45 and input to the AND circuit 46. A
In the ND circuit 46, the output of the inverter 45 and the output of the comparator circuit 44 are ANDed, and the output is input to the shift register 47. A system clock signal is input from the system clock input terminal 88 to the 2 ^n- bit shift register 47,
The data output of the shift register 47 is input to the latch circuit 48, and the data is held at the rising edge of the comparator circuit 43. Therefore, also in this embodiment, as in the case of the first embodiment, a signal proportional to the rise time of the received transmission path signal can be obtained. However, this latch circuit 48
Is different from the code in the first embodiment, the control signal code-converted by the code converter 49 is output from the control signal output terminal 89 and the timing extraction shown in FIG. By inputting to the circuit 2, that is, the control signal input terminal 82 of FIG. 2B and controlling and adjusting the delay amount of the delay circuit 28, the same effect as in the case of the first embodiment can be obtained. .

[0021]

As described above, according to the present invention, by providing the means for correcting the phase of the transmission signal according to the rise time of the reception signal, the data transmission line by the point-to-multipoint connection is provided. Also, there is an effect that it is possible to prevent line failures including data error and loss of synchronization in the main station due to the distance difference between the terminal devices.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram of an example of a line receiver circuit and a block diagram of an example of a timing extraction circuit in the embodiment.

FIG. 3 is an operation waveform diagram in the line receiver circuit.

FIG. 4 is an operation waveform diagram in the timing extraction circuit.

FIG. 5 is a circuit diagram of another example of the line receiver circuit in the embodiment.

FIG. 6 is a block diagram showing a conventional example, a circuit diagram of a line receiver circuit, and a block diagram of a timing extraction circuit.

FIG. 7 is an operation waveform diagram in the conventional line receiver circuit.

FIG. 8 is a conceptual block diagram showing a configuration of point-to-multipoint connection.

[Explanation of symbols]

1, 51 Line receiver circuit 2, 52 Timing extraction circuit 3, 53 Frame synchronization circuit 4, 54 Multiplexing / demultiplexing circuit 5, 55 Line driver circuit 6, 31, 56 Transformer circuit 7, 8, 18, 19, 32, 33, 43, 44, 63,
64 comparator circuits 9 to 17, 26, 34 to 42, 50, 57 to 62, 65
Resistance 20, 45 Inverter 21, 22, 46 AND circuit 23 Counter circuit 24, 48 Latch circuit 25 Decode circuit 27, 66 Phase comparison circuit 28 Delay circuit 29, 67 Loop filter 30, 68 Frequency divider circuit 47 Shift register 49 Code conversion Circuit 69 Main station 70-1, 70-2 Terminal device

Claims (2)

[Claims] 1. A line receiver circuit for receiving and decoding a transmission path signal and outputting a predetermined digital signal, and a timing for receiving an output of the line receiver circuit, extracting a clock signal from the output, and outputting the clock signal. An extraction circuit, a frame synchronization circuit that inputs a digital signal included in the output of the line receiver circuit, and outputs a frame synchronization signal via the clock signal, the digital signal, the clock signal, the frame synchronization signal, and a predetermined signal A multiplexer / demultiplexer circuit that receives transmission data and generates and outputs a transmission data string for transmission output and a reception data string for an internal circuit, and a line that receives the transmission data string and generates and outputs a transmission line signal .A driver circuit and a clock signal output from the timing extraction circuit. Receiving a time control signal proportional to the rise time of the transmission path signal generated in the line receiver circuit, and generating a time shift clock signal whose timing is controlled by the time control signal from the timing extraction circuit. A synchronous data transmission device characterized by outputting. 2. A clock signal extracted from the output of the line receiver circuit by the timing extraction circuit,
A phase comparator for comparing the phase with a delayed clock signal obtained by delaying the phase of the time shift clock signal output from the timing extraction circuit, and inputting the phase difference information output from the phase comparator, A loop filter that removes and outputs a high-frequency component included in the phase difference information; a frequency divider circuit that receives the output of the loop filter and controls and adjusts a frequency division ratio to output the time shift clock signal; 2. A delay circuit, the delay amount of which is controlled by a time control signal output from a line receiver circuit, which delays the phase of the time shift clock signal to generate and output the delayed clock signal. Frame synchronization circuit.