JPS6392048A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6392048A JPS6392048A JP61237467A JP23746786A JPS6392048A JP S6392048 A JPS6392048 A JP S6392048A JP 61237467 A JP61237467 A JP 61237467A JP 23746786 A JP23746786 A JP 23746786A JP S6392048 A JPS6392048 A JP S6392048A
- Authority
- JP
- Japan
- Prior art keywords
- die pad
- lead
- solder
- die
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 229910000679 solder Inorganic materials 0.000 claims abstract description 17
- 230000002265 prevention Effects 0.000 claims description 4
- 238000004080 punching Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 description 8
- 230000007547 defect Effects 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この考案はリードフレームのダイパッド上にダイを半田
ボンディングする半導体装着の改良に関するものである
。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] This invention relates to an improvement in semiconductor mounting in which a die is solder-bonded onto a die pad of a lead frame.
従来のこの種の半導体装置を第２図に従って説明する。 A conventional semiconductor device of this type will be explained with reference to FIG.
図において（１）は周知の工０リードフレーム（以下、
単にリードフレームと−う。）で、インナーリード（Ｉ
ＪＬ） 、成形金型（図示せず）でインナーリード（１
ｍ）より所定の深さ沈められたダイパッド（ｌｂ）、該
ダイパッド（１ｂ）を支持する宙吊りリード（ｌｏ）、
上記成形金型による成形時に宙吊りリート（ｌａ）のダ
イパッド近傍に形成される傾斜部（１（１）等で構成さ
れるものである。（２）は半田（３）を介しダイパッド
（ｌｂ）上に半田ボンディングされる工Ｏチップからな
るダイである。In the figure, (1) is a well-known lead frame (hereinafter referred to as
It's simply a lead frame. ), and the inner lead (I
JL), inner lead (1
a die pad (lb) sunk to a predetermined depth from m), a suspended lead (lo) supporting the die pad (1b),
The sloping part (1 (1), etc.) is formed near the die pad of the suspended reel (la) during molding with the above molding die. (2) is formed on the die pad (lb) through the solder (3). This is a die consisting of a processed O-chip that is solder-bonded to the die.
このように構成されたものにおいては、半田ボンディン
グ時の半田（３）の流れが傾斜部（１ｄ）で阻止される
。In this structure, the flow of solder (3) during solder bonding is blocked by the inclined portion (1d).
上記のような従来の半導体装置では、傾斜部（Ｘａ）の
形成はダイパッド（１ｂ）の沈め深さ寸法、管理上や、
リードフレーム（１）完成品単体の取り扱い上等の関係
からリードフレーム（１）バンキング時には行なわず、
半導体製造ライン中で行なわれるため、半導体製造の工
程が長くなるだけでなく、ダイパッド沈め装置を必要と
し、更には、ダイパッド沈め深さが変化すると、後工程
のワイヤボンディングの不良発生につながるため、上記
ダイパツド沈め深さの寸法管理が必要で、ダイパツド沈
め後のリードフレーム（１）の取り扱いに注意を要すだ
けでなく管理上極めて面倒である等の問題点を有してい
た。In the conventional semiconductor device as described above, the formation of the inclined portion (Xa) depends on the sinking depth dimension of the die pad (1b), management, etc.
Lead frame (1) Due to the handling of the finished product itself, lead frame (1) is not carried out during banking.
Because it is carried out in the semiconductor manufacturing line, it not only lengthens the semiconductor manufacturing process, but also requires a die pad sinking device.Furthermore, if the die pad sinking depth changes, it may lead to defects in wire bonding in the subsequent process. It is necessary to control the dimension of the die pad sinking depth, which not only requires careful handling of the lead frame (1) after the die pad is sunk, but also poses problems such as extremely troublesome management.
この発明は以上のような従来の実情に鑑みてなされたも
ので、製造工程の短縮や、製造不良を減少できる半導体
装置を提供するものである。The present invention has been made in view of the above-mentioned conventional circumstances, and it is an object of the present invention to provide a semiconductor device that can shorten the manufacturing process and reduce manufacturing defects.
この考案に係る半導体装直け、ダイパッドと、宙吊りリ
ードとが同一高さのままで、宙吊りリードのダイパッド
近傍に半田流れ止め手段を配設したものである。In the semiconductor device repair according to this invention, the die pad and the suspended lead remain at the same height, and a solder flow prevention means is provided in the vicinity of the die pad of the suspended lead.
この考案における半導体装置は、ダイボンディングに半
田の流れが半田流れ止め手段で■止され、ダイパッド沈
め装置が不要となる。In the semiconductor device according to this invention, the flow of solder during die bonding is stopped by the solder flow prevention means, and a die pad sinking device is not required.
以下、この考案の一実施例を第１図で説明する。 An embodiment of this invention will be described below with reference to FIG.
図において、（４）はリードフレームで、インナーリー
ド（４ａ）、該インナーリード（４ａ）と同一高さのダ
イパッド（４ｂ）、該ダイパッド（４ｂ）を支持する宙
吊りリード（４ｃ）、該宙吊りリード（４ｏ）のダイパ
ッド（４′ｂ）近傍に、リードフレーム（１］パンチン
グ時に形成されたＶノツチ（４ｄ）等で構成されるもの
である。In the figure, (4) is a lead frame, including an inner lead (4a), a die pad (4b) at the same height as the inner lead (4a), a suspended lead (4c) that supports the die pad (4b), and the suspended lead. It is composed of a V-notch (4d) formed near the die pad (4'b) of (4o) during punching of the lead frame (1).
なお、その他の符号の説明は第２図の説明と同一につき
省略する。Note that the description of other symbols is the same as the description of FIG. 2, and will therefore be omitted.
この考案は以上のように構成されているので、ダイ（２
）をダイパッド（４′ｂ）上だ半田（３）を介しボンデ
ィングする時の半田（３）の流れがＶノツチ（４ｄ）に
よって阻止される。又、Ｖノツチ（４ｄ）はリードフレ
ーム（１）パンチング時に形成しても、従来のように寸
法管理上の問題がないので、半導体製造工程を従来に比
し短かく出来、従来のダイパッド沈め装置も不要となる
。なお、半田流れ止め手段は上記Ｖノツチに限定される
ものではなく突起等でも良いことは言うまでもない。Since this idea is configured as described above, the die (2
) on the die pad (4'b) through the solder (3), the flow of the solder (3) is blocked by the V-notch (4d). In addition, even if the V-notch (4d) is formed when punching the lead frame (1), there is no problem in dimensional control as in the conventional method, so the semiconductor manufacturing process can be made shorter than the conventional die pad sinking equipment. is also no longer necessary. It goes without saying that the solder flow preventing means is not limited to the above-mentioned V-notch, but may also be a protrusion or the like.
この考案は以上のように、リードフレームのダイパッド
上にダイを半田ボンディングする半導体装置において、
ダイパッドと、宙吊りリードとが同一高さのままで、上
記宙吊りリードのダイパッド近傍に半田流れ止め手段を
配設したので、従来のように製造ライン中においてのダ
イパツド沈めが不要で、ダイパッド沈め装置を不要とな
り、半導体装置の製造工程が短縮される。又、従来の、
ようにダイパツド沈め深さが変化し不良になる等の心配
がなく、従来に比し製造不良要因が少なくなり生産性向
上に寄与できる等実用上極めて大なる効果がある。As described above, this idea is applicable to semiconductor devices in which a die is solder-bonded onto a die pad of a lead frame.
Since the die pad and the suspended lead remain at the same height and a solder flow prevention means is provided near the die pad of the suspended lead, there is no need to sink the die pad during the production line as in the conventional method, and the die pad sinking device can be used. This becomes unnecessary, and the manufacturing process of the semiconductor device is shortened. Also, conventional
In this way, there is no need to worry about defects due to changes in the depression depth of the die pad, and there are fewer causes of manufacturing defects than in the past, contributing to improved productivity, which is extremely effective in practical terms.
第１図はこの考案の一実施例を示す図、第２図は従来装
置を示す図である。
図において、（２）はダイ、（３）は半田、（４）けり
−ドフレーム、（４ａ）はインナーリード、（４ｂ）は
ダイバンド、（４０）は宙吊りリード、（４ｄ）けＶノ
ツチである０
なお、各図中、同一符号は同−又は相当部分を示す。FIG. 1 is a diagram showing an embodiment of this invention, and FIG. 2 is a diagram showing a conventional device. In the figure, (2) is the die, (3) is the solder, (4) is the keyed frame, (4a) is the inner lead, (4b) is the die band, (40) is the suspended lead, and (4d) is the V-notch. 0 In each figure, the same reference numerals indicate the same or corresponding parts.
Claims (2)
ディングするものにおいて、ダイパッドと、宙吊りリー
ドとが同一高さのままで、宙吊りリードのダイパッド近
傍に半田流れ止め手段を配設したことを特徴とする半導
体装置。(1) In a device in which a die is solder bonded onto a die pad of a lead frame, the die pad and the suspended lead remain at the same height, and a solder flow prevention means is provided near the die pad of the suspended lead. Semiconductor equipment.
又は突起からなる半田流れ手段としたことを特徴とする
特許請求の範囲第１項記載 の半導体装置。(2) A semiconductor device according to claim 1, characterized in that the solder flow means comprises a recess or a protrusion formed during punching of the lead frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61237467A JPS6392048A (en) | 1986-10-06 | 1986-10-06 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61237467A JPS6392048A (en) | 1986-10-06 | 1986-10-06 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6392048A true JPS6392048A (en) | 1988-04-22 |
Family
ID=17015764
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61237467A Pending JPS6392048A (en) | 1986-10-06 | 1986-10-06 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6392048A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04196574A (en) * | 1990-11-28 | 1992-07-16 | Mitsubishi Electric Corp | Lead frame |
-
1986
- 1986-10-06 JP JP61237467A patent/JPS6392048A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04196574A (en) * | 1990-11-28 | 1992-07-16 | Mitsubishi Electric Corp | Lead frame |
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