JPS6230355A - Lead frame for ic - Google Patents

Lead frame for ic

Info

Publication number
JPS6230355A
JPS6230355A JP16762185A JP16762185A JPS6230355A JP S6230355 A JPS6230355 A JP S6230355A JP 16762185 A JP16762185 A JP 16762185A JP 16762185 A JP16762185 A JP 16762185A JP S6230355 A JPS6230355 A JP S6230355A
Authority
JP
Japan
Prior art keywords
die pad
lead frame
lead
die
throttling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16762185A
Other languages
Japanese (ja)
Inventor
Akira Okamoto
岡本　曉
Hitoshi Akazawa
赤澤　均
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP16762185A priority Critical patent/JPS6230355A/en
Publication of JPS6230355A publication Critical patent/JPS6230355A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To remove a warpage by performing a DP throttling for applying a step to a die pad supporting piece for connecting die pads of an IC lead frame, and hitting between both ends of the throttled portion as well as the throttled portion and the die pad. CONSTITUTION:If the length Dy of a die pad 4 is remarkably shorter than a distance L between throttled portions of a die bad supporting piece 5 and the die pad is lowered with respect to the lead by a DP throttling by applying a step H, even if hittings A, C and D, B are applied to the both ends (a), (c) and (d), (b) of the throttled portion, a warpage generated by the throttling cannot be sufficiently removed. Then, hittings E, F are performed between the ends (c), (d) of the throttled portion and the pad 4. Thus, the warpage due to the throttling can be sufficiently corrected to obtain an IC lead frame having an accurate step H between the upper surface of the die pad and the upper surface of the lead.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明はＩＣ用リードフレームの改良に係わる。[Detailed description of the invention] <Industrial application field> The present invention relates to improvements in lead frames for ICs.

〈従来の技術〉 ■Ｃ用リードフレーム中央のダイパット上にグイポンド
されたＩＣチップ周−Ｔ２の端子とリード詳と金線等で
ワイヤポンディングする際、ワイヤポンディング用金線
使用量の削減、金線同志の接触による不良率の低減を図
るため、リードフレームのダイパット支持片にＤＰ（デ
ィンプル）加工を施してリード面よりダイパット面を低
めて段差をつけることが行なわれる。第２図（ａ）はこ
のようなＩＣ用リードフレームの平面図であり、第２図
（ｂ）は第２図（ａ）に示すもののダイパット部分の側
面図である。７ｆＳ２図（ａ）において、■はリードフ
レーム外枠、２ａはインナーリード、２ｂはアウターリ
ード、３はリードを保持するタイ／ヘー。<Conventional technology> ■When wire bonding the circumference of the IC chip on the die pad in the center of the C lead frame - T2 terminals and lead details with gold wire, etc., the amount of gold wire used for wire bonding can be reduced. In order to reduce the defective rate due to contact between gold wires, the die pad support piece of the lead frame is subjected to DP (dimple) processing to lower the die pad surface below the lead surface to form a step. FIG. 2(a) is a plan view of such an IC lead frame, and FIG. 2(b) is a side view of a die pad portion of the lead frame shown in FIG. 2(a). In Figure 7fS2 (a), ■ is the outer frame of the lead frame, 2a is the inner lead, 2b is the outer lead, and 3 is the tie/hook that holds the lead.

４はダイパット、５はダイパットを支持する支持片であ
る。第２図　（ｂ）はダイパットとリードフレームとの
関係を示す、ダイパット部分の側面図である。第２図（
ｂ）に示す如く、リードフレームの外枠１から突出した
ダイパット支持片５は、ａ、Ｃ及びｄ、ｂ間でＤＰ加工
の絞り加工が施され、ダイパット４の上面はインナーリ
ード２ａの上面に対しＨの段差が与えられ、低くなって
いる。尚、ＤＰ加工の絞り加工をダイパット支持片に施
すと、絞り加工部の肉の一部が両側へ逃る結果、加工治
具を外すとダイパット支持片にそりを生ずる。これを防
止するため、ａ、ｃ、ｄ、ｂの肩の部分に第３図に示す
ようにたたきＡ、Ｃ。4 is a die pad, and 5 is a support piece that supports the die pad. FIG. 2(b) is a side view of the die pad portion showing the relationship between the die pad and the lead frame. Figure 2 (
As shown in b), the die pad support piece 5 protruding from the outer frame 1 of the lead frame is drawn by DP processing between a, C, d, and b, so that the upper surface of the die pad 4 is on the upper surface of the inner lead 2a. On the other hand, a height difference of H is given, making it lower. Note that when the die pad support piece is subjected to the drawing process of the DP process, a portion of the flesh of the drawn portion escapes to both sides, and as a result, when the processing jig is removed, the die pad support piece is warped. To prevent this, tap A and C on the shoulders of a, c, d, and b as shown in Figure 3.

Ｄ、Ｂを入れることによって絞り加工によるそりを矯正
している。By adding D and B, the warp caused by the drawing process is corrected.

〈発明が解決しようとする問題点） 第３図に示す如く、ＩＣ用リードフレームのダイパット
４をリード２の高さに対しＨだけ段差をつけるため、絞
り加工とこれによるそりを矯ｉＥするたたきを加えて加
工していたが、リードフレームの多ビン化に伴ない、ダ
イパット４を支えるダイパット支持片の長さ、即ち絞り
加工間の距離りが、ダイパットの長さ［］ｙに比べて相
当に長くなり、第３図に示すようなａ、ｃ、ｄ、ｂ部分
だけのたたきでは絞り加工によるそりが第４図に示すよ
うに、とり切れず、ダイパット４のリード２ａに対する
所望の段差Ｈが得られないことが分った。このようにダ
イパット支持片の長さがダイパットの支持片の方向の長
さＤＹに比べて特に長いものに対して、改良が必要とな
った。<Problems to be Solved by the Invention> As shown in Fig. 3, in order to make the die pad 4 of the IC lead frame step by an amount H with respect to the height of the lead 2, a drawing process and a beating process are performed to correct the warpage caused by the drawing process. However, as the number of bins for lead frames increases, the length of the die pad support piece that supports the die pad 4, that is, the distance between drawing operations, is considerably larger than the length of the die pad []y. If only the parts a, c, d, and b as shown in FIG. It turned out that I couldn't get it. As described above, it has become necessary to improve the die pad support piece which is particularly long compared to the length DY of the die pad support piece in the direction of the die pad support piece.

本発明はかかる従来技術の問題点に鑑みてなされたもの
で、ＩＣ用リードフレームのグイバントのＤＰ加工によ
るそりを取り除く、有効なたたきを施した。ＩＣ用リー
ドフレームを提供することを目的としている。The present invention has been made in view of the problems of the prior art, and provides effective beating to remove the warpage caused by DP processing of the lead frame for IC. Its purpose is to provide lead frames for ICs.

〈問題点を解決するための手段〉 かかる目的を達成した本発明によるＩＣ用リードフレー
ムの構成は、ＩＣ用リードフレームのダイパット上面を
リード上面に対して段差をつけて低めたＩＣ用リードフ
レームにおいて、」二足ＩＣ用リードフレームのダイパ
ットをつなぐダイパット支持片に、上記段差を与えるた
めのＤＹ絞り加工を施すとともに、該絞り加工部の両端
部ならびに、該絞り加工部と上記ダイパットの間にたた
きを入れたことを特徴とするものである。<Means for Solving the Problems> The structure of the IC lead frame according to the present invention which achieves the above object is that the IC lead frame has a die pad upper surface lowered by a step with respect to the lead upper surface. , "A die pad support piece that connects the die pads of a bipedal IC lead frame is subjected to a DY drawing process to provide the above-mentioned step, and a DY drawing process is applied to both ends of the drawn part and between the drawn part and the die pad. It is characterized by the inclusion of.

〈実施例） 本発明によるＩＣ用リードフレームの一実施例を図面に
よって説明する。第１図（ａ）は本発明によるＩＣ用リ
ードフレームのダイパットとダイパット支持片部分の平
面図である。第１図（ｂ）は第１図（ａ）に示すものの
側面図である。<Example> An example of an IC lead frame according to the present invention will be described with reference to the drawings. FIG. 1(a) is a plan view of a die pad and a die pad support piece portion of an IC lead frame according to the present invention. FIG. 1(b) is a side view of what is shown in FIG. 1(a).

特に多ピン用ＩＣのリードフレームにおいては、ダイパ
ット４の長さｏｙがダイパット支持片５の絞り加工間の
距＃、、Ｌに比べて著しく短かくなる。このような場合
、ＤＹ絞り加工によってダイパットをリードに対して段
差Ｈを与えて低くする場合、第４図で説明した通り、従
来のものでは、絞り加工の両端、ａ、ｃ及びｄ、ｂのみ
にたたき、Ａ、Ｃ及びり、Ｂを施しただけでは、絞り加
工によって生じたそりを充分に取り除くことができなか
った。そこで更に、絞り加工の端部ｃ、ｄとダイパット
４の間のただきＥ、Ｆを施した所、第１図（ａ）に示す
如く絞り加工によるそりは充分に矯正され、ダイパット
上面とリード上面との間に精度の高い段差ＨをもつＩＣ
用リードフレームを得ることができた０本発明によるＩ
Ｃ用リードフレームの実験例を以下に示す。Particularly in the lead frame of a multi-pin IC, the length oy of the die pad 4 is significantly shorter than the distance #, L between the drawing processes of the die pad support piece 5. In such a case, when lowering the die pad by giving a step H to the lead by DY drawing, as explained in Fig. 4, in the conventional method, only the ends a, c, d, and b of the drawing process are used. It was not possible to sufficiently remove the warpage caused by the drawing process only by pounding, A, C, drilling, and B. Then, the warpage caused by the drawing process was sufficiently corrected, and the warpage caused by the drawing process was sufficiently corrected at the places where the edges E and F were applied between the ends c and d of the drawing process and the die pad 4, as shown in FIG. 1(a). IC with a highly accurate step H between the top surface and the top surface
According to the present invention, it was possible to obtain a lead frame for
An experimental example of a lead frame for C is shown below.

ＩＣ用リードフレームの素材は厚さ０．２５ａｗｗの４
２合金が用いられた。ＩＣ用リードフレームの絞り加工
間の距＃Ｌは、Ｌ＝１５ｍｍ、タイパントのＲさＤＹは
、Ｑｙ＝６閣、リードとＤＰ加工されたグイ±０．０３ バットの段差ＨはＨ＝０．３　　　ｍと規定されたもの
に対し、次表のたたき寸法のものが第１図（ａ）。The material of the IC lead frame is 4 with a thickness of 0.25 aww.
Two alloys were used. The distance #L between the drawing processes of the IC lead frame is L = 15 mm, the radius DY of the tie pant is Qy = 6 mm, the lead and the DP processed guide are ±0.03, and the step H of the butt is H = 0. In contrast to those specified as 3 m, those with the dimensions shown in the table below are shown in Figure 1 (a).

（ｂ）に示す６箇所Ａ、Ｂ、Ｃ，Ｄ、Ｅ、Ｆに施された
。It was applied to six locations A, B, C, D, E, and F shown in (b).

表 この結果、ダイパット上面とリード上面との段差Ｈは Ｈ＝　０．２８〜０．３２ｍ＋となり、与えられたＨの
許容範囲に納まった。As a result, the height difference H between the top surface of the die pad and the top surface of the leads was H=0.28 to 0.32 m+, which was within the given tolerance range of H.

参考までにただきＥ、Ｆを施さない場合の段差Ｈ°を示
すと、 Ｈ’　＝０．２３〜０．３０＋ｌｌ１１で、所望の段差
が得られないことが分る。For reference, the level difference H° in the case where E and F are not applied shows that H'=0.23 to 0.30+ll11, and the desired level difference cannot be obtained.

〈発明の効果〉 本発明によるＩＣ用リードフレームによれば、グイパン
ト部を支持するダイパット支持片がとくに長いものにお
いて、ＤＰ絞り加工によるそりを矯正するためのたたき
を、絞り加工端部の外に更に、絞り加工端部とダイパッ
トとの間に施したことによって、そりが矯正され、精度
の高いダイパットの段差をもつＩＣ用リードフレームが
得られた。これによって、ＩＣ用リードフレームのダイ
パットの段差のばらつきが少なくなり、ダイパット」ユ
のＩＣチップの端子群とリードとのワイヤポンディング
の作業の信頼性が一段と向−ヒされ、優れた品質のＩＣ
製品が得られるようになった。<Effects of the Invention> According to the IC lead frame according to the present invention, when the die pad support piece that supports the guide pant part is particularly long, the beating for correcting the warp due to the DP drawing process is not applied to the outside of the drawing process end. Furthermore, by applying the drawing process between the end of the drawing process and the die pad, the warpage was corrected, and an IC lead frame with highly accurate die pad steps was obtained. As a result, variations in the steps of the die pad of the IC lead frame are reduced, and the reliability of the wire bonding work between the terminal group and the lead of the IC chip on the die pad is further improved.
The product is now available.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）は本発明によるＩＣ用リードフレームのダ
イパット部分の平面図、第１図（ｂ）は第１図（ａ）に
示すものの側面図、第２図（ａ）はＩＣ用リードフレー
ムの平面図、第２図（ｂ）は第２図（ａ）に示すものの
ダイパット部分の側面図、第３図及び第４図は従来のＩ
Ｃ用、リードフレームのダイパット支持片のＤＰ絞り加
工を説明する図である・ 図面中。 ４はダイパット、５はダイノくット支持片、Ａ、ＢＢ、
Ｃ，Ｄ、Ｅ、Ｆはたたき加工部分である。FIG. 1(a) is a plan view of the die pad portion of the IC lead frame according to the present invention, FIG. 1(b) is a side view of the die pad part shown in FIG. 1(a), and FIG. 2(a) is the IC lead. A plan view of the frame, FIG. 2(b) is a side view of the die pad part of the frame shown in FIG. 2(a), and FIGS. 3 and 4 are the conventional I
This is a diagram illustrating the DP drawing process of the die pad support piece of the lead frame for C. 4 is a die pad, 5 is a die pad support piece, A, BB,
C, D, E, and F are the pounded parts.

Claims (1)

【特許請求の範囲】[Claims] ＩＣ用リードフレームのダイパット上面をリード上面に
対して段差をつけて低めたＩＣ用リードフレームにおい
て、上記ＩＣ用リードフレームのダイパットをつなぐダ
イパット支持片に上記段差を与えるためのＤＰ絞り加工
を施すとともに、該絞り加工部の両端部ならびに、該絞
り加工部と上記ダイパットの間にたたきを入れたことを
特徴とするＩＣ用リードフレーム。In an IC lead frame in which the top surface of the die pad of the IC lead frame is lowered by creating a step with respect to the top surface of the lead, a DP drawing process is applied to the die pad support piece that connects the die pad of the IC lead frame to provide the step. A lead frame for an IC, characterized in that a punch is provided at both ends of the drawn portion and between the drawn portion and the die pad.
JP16762185A 1985-07-31 1985-07-31 Lead frame for ic Pending JPS6230355A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16762185A JPS6230355A (en) 1985-07-31 1985-07-31 Lead frame for ic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16762185A JPS6230355A (en) 1985-07-31 1985-07-31 Lead frame for ic

Publications (1)

Publication Number Publication Date
JPS6230355A true JPS6230355A (en) 1987-02-09

Family

ID=15853181

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16762185A Pending JPS6230355A (en) 1985-07-31 1985-07-31 Lead frame for ic

Country Status (1)

Country Link
JP (1) JPS6230355A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01130551A (en) * 1987-11-17 1989-05-23 Toshiba Corp Manufacture of lead frame for semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01130551A (en) * 1987-11-17 1989-05-23 Toshiba Corp Manufacture of lead frame for semiconductor device

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