JPS639142U - - Google Patents
Info
- Publication number
- JPS639142U JPS639142U JP10161986U JP10161986U JPS639142U JP S639142 U JPS639142 U JP S639142U JP 10161986 U JP10161986 U JP 10161986U JP 10161986 U JP10161986 U JP 10161986U JP S639142 U JPS639142 U JP S639142U
- Authority
- JP
- Japan
- Prior art keywords
- package
- flat
- metal plate
- common terminals
- chips
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 238000009434 installation Methods 0.000 description 2
Description
第１図はこの考案の一実施例を示す構成説明図
、第２図は第１図の実施例の取り付け状況を示す
説明図、第３図は従来例を示す構成説明図、第４
図は従来例の第２図対応図、第５図および第６図
は従来例の取り付け状態を示す説明図である。
１１……フラツトパツケージ型ＩＣ、１２……
パツケージ、１２ａ……平坦面、１３……チツプ
、１４……外部接続用端子、１４ａ……共通端子
用金属板、１５……配線用基板、１６ａ，１６ｂ
……ビス、１７……基台。
Fig. 1 is a structural explanatory diagram showing one embodiment of this invention, Fig. 2 is an explanatory drawing showing the installation situation of the embodiment of Fig. 1, Fig. 3 is a structural explanatory diagram showing a conventional example, and Fig. 4
The figure is a diagram corresponding to FIG. 2 of the conventional example, and FIGS. 5 and 6 are explanatory diagrams showing the installation state of the conventional example. 11...Flat package type IC, 12...
Package, 12a... Flat surface, 13... Chip, 14... External connection terminal, 14a... Metal plate for common terminal, 15... Wiring board, 16a, 16b
...Bis, 17...base.
Claims (1)
金属板と、各チツプに接続される各外部接続用端
子の一端とをパツケージに収容し、共通端子用金
属板の端子部と各外部接続用端子の他端をパツケ
ージ外部に露出させて固定したフラツトパツケー
ジ型ＩＣにおいて、 パツケージの外面に取付用平坦面を備え、共通
端子用金属板を延出してパツケージの両側に露出
させ、その各露出部分に前記平坦面に対して垂直
に貫通する取付用穴を開口したことを特徴とする
フラツトパツケージ型ＩＣ。[Scope of Claim for Utility Model Registration] A package contains a plurality of chips, a metal plate for common terminals on which the chips are mounted, and one end of each external connection terminal connected to each chip, and a metal plate for common terminals is housed in a package. In a flat package type IC in which the terminal part and the other end of each external connection terminal are exposed and fixed to the outside of the package, a flat mounting surface is provided on the outer surface of the package, and a metal plate for common terminals is extended to attach to both sides of the package. 1. A flat package type IC, characterized in that each exposed portion is provided with a mounting hole penetrating perpendicularly to the flat surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10161986U JPS639142U (en) | 1986-07-02 | 1986-07-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10161986U JPS639142U (en) | 1986-07-02 | 1986-07-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS639142U true JPS639142U (en) | 1988-01-21 |
Family
ID=30972509
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10161986U Pending JPS639142U (en) | 1986-07-02 | 1986-07-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS639142U (en) |
-
1986
- 1986-07-02 JP JP10161986U patent/JPS639142U/ja active Pending
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