JPS639126A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS639126A JPS639126A JP15169086A JP15169086A JPS639126A JP S639126 A JPS639126 A JP S639126A JP 15169086 A JP15169086 A JP 15169086A JP 15169086 A JP15169086 A JP 15169086A JP S639126 A JPS639126 A JP S639126A
- Authority
- JP
- Japan
- Prior art keywords
- silicon oxide
- oxide film
- plasma silicon
- film
- deposited
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 44
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 44
- 239000011229 interlayer Substances 0.000 claims abstract description 8
- OEYIOHPDSNJKLS-UHFFFAOYSA-N choline Chemical compound C[N+](C)(C)CCO OEYIOHPDSNJKLS-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229960001231 choline Drugs 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 7
- 239000007864 aqueous solution Substances 0.000 claims abstract description 4
- 238000000151 deposition Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 6
- 239000010410 layer Substances 0.000 abstract description 13
- 238000000034 method Methods 0.000 abstract description 10
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract description 6
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 abstract description 5
- 230000002159 abnormal effect Effects 0.000 abstract description 3
- 230000008021 deposition Effects 0.000 abstract description 3
- IJJWOSAXNHWBPR-HUBLWGQQSA-N 5-[(3as,4s,6ar)-2-oxo-1,3,3a,4,6,6a-hexahydrothieno[3,4-d]imidazol-4-yl]-n-(6-hydrazinyl-6-oxohexyl)pentanamide Chemical compound N1C(=O)N[C@@H]2[C@H](CCCCC(=O)NCCCCCC(=O)NN)SC[C@@H]21 IJJWOSAXNHWBPR-HUBLWGQQSA-N 0.000 abstract 1
- 239000012535 impurity Substances 0.000 description 9
- 238000004140 cleaning Methods 0.000 description 7
- 239000012459 cleaning agent Substances 0.000 description 5
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 4
- 239000005380 borophosphosilicate glass Substances 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 239000000428 dust Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 238000005406 washing Methods 0.000 description 3
- 230000005856 abnormality Effects 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000013517 stratification Methods 0.000 description 1
- 229910021642 ultra pure water Inorganic materials 0.000 description 1
- 239000012498 ultrapure water Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
この発明は、半導体装置の製造方法に関し、更に詳しく
は、多ＷＡｌｉｉ！線の層間絶縁膜を形成する場合に特
に好適な、低温プラズマシリコン酸化膜の堆積前の洗浄
処理に係るものである。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a method for manufacturing a semiconductor device. The present invention relates to a cleaning process before the deposition of a low-temperature plasma silicon oxide film, which is particularly suitable for forming a line interlayer insulating film.
（従来の技術）
多層配置構造の居間絶縁膜として、最近では低温プラズ
マＣＶＤ法によって形成されるプラズマシリコン酸化膜
が用いられている。(Prior Art) Recently, a plasma silicon oxide film formed by a low-temperature plasma CVD method has been used as a living room insulating film having a multilayer arrangement structure.
添付図は多層配線構造の半導体装置（この場合はＭＯＳ
ＦＥＴ）を製造する工程の一部を示したものである
。The attached diagram shows a semiconductor device with a multilayer wiring structure (in this case, MOS
This figure shows part of the process of manufacturing FET.
第１図において、１は半導体基板（１ａ及び１ｂはソー
ス及びドレインとなるＮ型領域）、２は素子分離領域、
３はゲート酸化膜、４はゲート酸化膜３上に形成された
多結晶シリコン製のゲート電極、５は半導体基板１の表
面及びゲート電極４の上にプラズマＣＶＤ法によって堆
積されたシリコン酸化膜、６はシリコン酸化膜５上に形
成しりフローにより平坦化されたＢＰＳＧＩＩ（ホウ素
りんガラス模）である。 なお、第１図に至るまでの製
造工程の説明を省略する。In FIG. 1, 1 is a semiconductor substrate (1a and 1b are N-type regions that become the source and drain), 2 is an element isolation region,
3 is a gate oxide film; 4 is a polycrystalline silicon gate electrode formed on the gate oxide film 3; 5 is a silicon oxide film deposited on the surface of the semiconductor substrate 1 and on the gate electrode 4 by plasma CVD; 6 is a BPSG II (boron phosphorus glass pattern) formed on the silicon oxide film 5 and flattened by an edge flow. Note that the explanation of the manufacturing process up to FIG. 1 will be omitted.
第１図の状態になった後、公知のホトエツチング（ＰＥ
Ｐ）に−よってＢＰＳＧ膜６とシリコン酸化１１５にコ
ンタクミーホールを開口し、次いで不図示のレジストの
剥離、Ａ１膜准積、ＡｌｇＩのホトエツチングを、この
順序で行うことにより、第２図に示されるように、コン
タクトホール内に入る第一層配線７をＢＰＳＧ膜６上に
形成する。After reaching the state shown in Figure 1, known photo etching (PE) is applied.
A contact hole is opened in the BPSG film 6 and the silicon oxide 115 by step P), and then the resist (not shown) is removed, the A1 film is deposited, and the AlgI is photoetched in this order. A first layer wiring 7 is formed on the BPSG film 6 so as to enter the contact hole.
次に、Ａ１の第一層配線７表面が露出している第２図の
状態の表面を、超純水による流水で洗浄した後、まず、
第３図に示すように第一のプラズマシリコン酸化膜８を
堆積し、更にその上にレジスト９を平坦になるように塗
布する。 しかる後、レジスト９のエツチング速度と第
一のプラズマシリコン酸化膜８のエツチング速度が等し
くなるようにエツチング条件を制御しつつ、反応性イオ
ンエツチング（ＲＩＥ）によってレジスト９を第一のプ
ラズマシリコン酸化膜８の露出表面がほぼ平坦となるま
でエッチバックすると、第４図の状態に至る。Next, after washing the surface of A1 in the state shown in FIG. 2 where the surface of the first layer wiring 7 is exposed with running ultrapure water, first,
As shown in FIG. 3, a first plasma silicon oxide film 8 is deposited, and a resist 9 is further applied thereon so as to be flat. Thereafter, the resist 9 is etched into the first plasma silicon oxide film by reactive ion etching (RIE) while controlling the etching conditions so that the etching rate of the resist 9 is equal to the etching rate of the first plasma silicon oxide film 8. When the exposed surface of 8 is etched back until it becomes almost flat, the state shown in FIG. 4 is reached.
第４図の状態では、第一のプラズマシリコン酸化膜８の
露出表面にレジスト９の残漬やごみ等の不純物１０が付
着しているので、これらの不純物１０を除去するために
第４図の状態の半導体基板を酸素プラズマ雰囲気に入れ
て該不純物１０を燃焼させた後、第一のプラズマシリコ
ン酸化膜８の表面を流水洗浄する。In the state shown in FIG. 4, impurities 10 such as residual resist 9 and dust are attached to the exposed surface of the first plasma silicon oxide film 8. In order to remove these impurities 10, the steps shown in FIG. After the semiconductor substrate in this state is placed in an oxygen plasma atmosphere to burn off the impurities 10, the surface of the first plasma silicon oxide film 8 is washed with running water.
そして、流水洗浄後の第一のプラズマシリコン酸化膜８
の上に、第５図に示すように第二のプラズマシリコン酸
化１１１１１を堆積した後、ＰＥＰを行って第二のプラ
ズマシリコン酸化１１１と第一のプラズマシリコン余化
ｌｌ５Ｉ８にコンタクトホールを開口する。 そして不
図示のレジスト剥離後に第二層配線用のＡ１膜を堆積さ
せた後、ＰＥＰによってＡ１膜をパターニングして第二
層配線１２を完成させる。Then, the first plasma silicon oxide film 8 after washing with running water
After depositing a second plasma silicon oxide 11111 on the substrate as shown in FIG. 5, PEP is performed to open contact holes in the second plasma silicon oxide 111 and the first plasma silicon oxide 11118. After removing the resist (not shown), an A1 film for the second layer wiring is deposited, and then the A1 film is patterned by PEP to complete the second layer wiring 12.
前記のごとき製造方法では、第一のプラズマシリコン酸
化ｇ１８（すなわち、層間絶縁膜の下層部分）の上に第
二のプラズマシリコン酸化膜１１（すなわち、層間絶縁
膜の上層部分）を堆積させる前にレジスト９と第一のプ
ラズマシリコン酸化ｌｌ１８とをＲＩＥによってエッチ
バックしているので層間絶縁膜の表面（すなわち、第二
のプラズマシリコン酸化１！１１の表面）が平坦になり
、該層間絶縁膜の上を被覆する第二層配線１２に段切れ
が生じないという利点があるが、次のような問題点があ
った。In the above manufacturing method, before depositing the second plasma silicon oxide film 11 (i.e., the upper layer part of the interlayer insulating film) on the first plasma silicon oxide film 18 (i.e., the lower layer part of the interlayer insulating film), Since the resist 9 and the first plasma silicon oxide 118 are etched back by RIE, the surface of the interlayer insulating film (that is, the surface of the second plasma silicon oxide 1!11) becomes flat, and the surface of the interlayer insulating film becomes flat. Although there is an advantage that no break occurs in the second layer wiring 12 covering the top, there are the following problems.
前記のごとき従来方法では、第二のプラズマシリコン酸
化ＩＩ！６１１を堆積させる前に第一のプラズマシリコ
ン酸化膜８のエッチバック表面を流水洗浄しているが、
流水洗浄後の該表面を精査してみると、レジスト残渣等
の不純物１０が完全に除去されておらず、その結果、該
表面に第二のプラズマシリコン酸化膜１１を堆積させる
と該表面の残留不純物を核としてプラズマシリコン酸化
膜１１が局所的に異常成長して該膜１１の表面の平坦性
が著しく損われるという現象が発生していた。In the conventional method as described above, the second plasma silicon oxidation II! Before depositing 611, the etched back surface of the first plasma silicon oxide film 8 was washed with running water.
A close examination of the surface after washing with running water revealed that impurities 10 such as resist residues were not completely removed, and as a result, when the second plasma silicon oxide film 11 was deposited on the surface, the remaining residue on the surface A phenomenon has occurred in which the plasma silicon oxide film 11 locally grows abnormally using impurities as nuclei, and the flatness of the surface of the film 11 is significantly impaired.
このような残漬不純物を除去するためには、希ＨＦとＮ
Ｈ，Ｆとを用いて洗浄することも考えられるが、この洗
浄剤はプラズマシリコン酸化膜を侵しまた段差部分など
でエツチングレートが変化するので好ましいものではな
い。In order to remove such residual impurities, dilute HF and N
Although it is possible to use H or F for cleaning, this cleaning agent is not preferable because it attacks the plasma silicon oxide film and changes the etching rate at stepped portions.
また、希ＨＦ、！：ＮＨ，Ｆの洗浄剤の代わりに過酸化
水素と硫酸の洗浄剤を用いることも考えられているが、
過酸化水素と硫酸の洗浄剤はＡ１配線を激しく腐食して
しまうので用いることはできない。Also, Nozomi HF! :Using hydrogen peroxide and sulfuric acid cleaning agents instead of NH and F cleaning agents has been considered, but
Hydrogen peroxide and sulfuric acid cleaning agents cannot be used because they severely corrode the A1 wiring.
（発明が解決しようとする問題点）
この発明の目的は、低温プラズマシリコン酸化膜を堆積
させようとする表面を完全に清浄化することによって堆
積させた上層の低温プラズマシリコン酸化膜に局所的異
常成層を防止することができる、改良された製造方法を
提供することである。(Problems to be Solved by the Invention) An object of the present invention is to completely clean the surface on which a low-temperature plasma silicon oxide film is to be deposited, thereby causing local abnormalities in the deposited upper low-temperature plasma silicon oxide film. An object of the present invention is to provide an improved manufacturing method that can prevent stratification.
［発明の構成］
（問題点を解決するための手段と作用）本発明方法は、
エッチバック後のプラズマシリコン酸化膜表面の不純物
を完全に除去するために種々の試みを行った結果、コリ
ン含有液を洗浄剤として用いることによって低；ｇプラ
ズマシリコン酸化膜を堆積しようとする表面の不純物を
完全に除去できるとともに他の膜や特にＡ１配線等に全
く河の損傷をも及ぼす恐れのないことが確認され、該前
処理をした復に該膜の堆積をすることによりその局所的
異常成長を防止するものである。[Structure of the invention] (Means and effects for solving the problems) The method of the present invention has the following features:
As a result of various attempts to completely remove impurities from the surface of the plasma silicon oxide film after etchback, we found that by using a choline-containing solution as a cleaning agent, a low; It has been confirmed that impurities can be completely removed and there is no risk of causing any damage to other films, especially the A1 wiring, etc., and by depositing the film after the pretreatment, local abnormalities can be removed. It prevents growth.
（実施例〉
本実施例の方法は、第１図乃至第４図に示した従来方法
のプロセスの後、第５図に示す段階においてエッチバッ
クしたプラズマシリコン酸化膜８の露出表面をコリンを
含有した液で洗浄することを特徴とする。(Example) In the method of this example, after the process of the conventional method shown in FIGS. 1 to 4, the exposed surface of the plasma silicon oxide film 8 that was etched back in the step shown in FIG. It is characterized by being washed with a solution of water.
本実施例の場合、層間絶縁膜の下層部分を構成する第一
のプラズマシリコン酸化膜８の表面をレジスト９ととも
にエッチバックして第４図の状態にした後、まず、従来
方法と同様にレジスト９の残漬を酸素プラズマ雰囲気中
で燃焼して取り除き、しかる後、コリン（０，１％）と
Ｈ２０２（０，４％）とを含有する水溶液を用いて該膜
８の露出表面を７０℃で１０分間洗浄し、更に純水で１
５分間リンスした。 この後、第一のプラズマシリコン
酸化膜８の上に第二のプラズマシリコン酸化膜１１を堆
積し、更に従来方法と同様に、コンタクトホールの間口
と上層配線の形成を行って第５図と同じ構造の半導体装
置を構成した。In the case of this embodiment, after etching back the surface of the first plasma silicon oxide film 8 constituting the lower part of the interlayer insulating film together with the resist 9 to obtain the state shown in FIG. The remaining residue of membrane 8 is removed by burning in an oxygen plasma atmosphere, and then the exposed surface of membrane 8 is heated at 70° C. using an aqueous solution containing choline (0.1%) and H202 (0.4%). Wash for 10 minutes with
Rinse for 5 minutes. After this, a second plasma silicon oxide film 11 is deposited on the first plasma silicon oxide film 8, and the frontage of the contact hole and the upper layer wiring are formed in the same manner as in the conventional method. A semiconductor device with this structure was constructed.
［発明の効果］
本発明方法の効果を確認するために、コリン含有液で洗
浄を行う館のプラズマシリコン酸化膜８のエッチバック
表面と、コリン含有液で洗浄後の該酸化膜８のエッチバ
ック表面とについて０．５μｍ以上の大きさの付着ごみ
の数を調査したところ、洗浄前には付着ごみが１５００
個程で６ったのに対し、洗浄後の残留ごみの数は１００
〜１５０個に減少しており、従って、洗浄によってごみ
の数が大幅に低減したことがわかった。 また、洗浄後
に堆積させたプラズマシリコン酸化膜の表面に異常な突
起が生じているかどうかを調べたところ、異常突起の吊
環は全くなかった。 更に上層配線完成後にオーブンシ
ョートイールドを調査したところ、３０％から９０％に
向上した。[Effects of the Invention] In order to confirm the effects of the method of the present invention, the etch-back surface of the plasma silicon oxide film 8 was cleaned with a choline-containing solution, and the etch-back surface of the oxide film 8 after cleaning with a choline-containing solution was examined. When we investigated the number of adhering dust with a size of 0.5 μm or more on the surface, we found that there were 1,500 adhering dust before cleaning.
The number of residual garbage after cleaning was 100, compared to 6.
Therefore, it was found that the number of debris was significantly reduced by cleaning. In addition, when we investigated whether abnormal protrusions had formed on the surface of the plasma silicon oxide film deposited after cleaning, we found that there were no hanging rings of abnormal protrusions. Furthermore, when the oven short yield was investigated after the upper layer wiring was completed, it was improved from 30% to 90%.
第１図乃至第５図は本発明方法に関連する半導体装Ｍ製
造工程の概略図である。
１・・・半導体基板、 ２・・・素子分離領域、 ３・
・・ゲート酸化膜、 ４・・・ゲート電極、 ５・・・
シリコン酸化膜、 ６・・・ＢＰＳＧ膜、 ７・・・第
一層配線、８・・・プラズマシリコン酸化膜、 ９・・
・レジスト、１ｏ・・・不純物、 １１・・・プラズマ
シリコン酸化膜、１２・・・第二層配線。
第１図
第２図
第３図1 to 5 are schematic diagrams of the manufacturing process of a semiconductor device M related to the method of the present invention. 1... Semiconductor substrate, 2... Element isolation region, 3.
...Gate oxide film, 4...Gate electrode, 5...
Silicon oxide film, 6... BPSG film, 7... First layer wiring, 8... Plasma silicon oxide film, 9...
・Resist, 1o... Impurity, 11... Plasma silicon oxide film, 12... Second layer wiring. Figure 1 Figure 2 Figure 3
Claims (1)
リコン酸化膜を堆積させるに際し、コリンを含有する水
溶液で堆積させるべき表面の前処理を行つた後に低温プ
ラズマシリコン酸化膜の堆積を行うことを特徴とする半
導体装置の製造方法。 ２ 堆積させるべき表面が、レジスト膜をエッチバック
することによって形成された平坦な第一の低温プラズマ
シリコン酸化膜の表面であり、該表面上に更に第二の低
温プラズマシリコン酸化膜を堆積し、積層された第一及
び第二の低温プラズマシリコン酸化膜が多層Ａｌ配線の
層間絶縁膜を構成する特許請求の範囲第１項記載の半導
体装置の製造方法。[Claims] 1. When directly or indirectly depositing a low-temperature plasma silicon oxide film on a semiconductor substrate, the surface to be deposited is pretreated with an aqueous solution containing choline, and then the low-temperature plasma silicon oxide film is deposited. 1. A method of manufacturing a semiconductor device, characterized in that: 2. The surface to be deposited is the flat surface of the first low-temperature plasma silicon oxide film formed by etching back the resist film, further depositing a second low-temperature plasma silicon oxide film on the surface, 2. The method of manufacturing a semiconductor device according to claim 1, wherein the laminated first and second low-temperature plasma silicon oxide films constitute an interlayer insulating film of a multilayer Al wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15169086A JPS639126A (en) | 1986-06-30 | 1986-06-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15169086A JPS639126A (en) | 1986-06-30 | 1986-06-30 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS639126A true JPS639126A (en) | 1988-01-14 |
Family
ID=15524132
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15169086A Pending JPS639126A (en) | 1986-06-30 | 1986-06-30 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS639126A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19521389A1 (en) * | 1994-12-06 | 1996-06-13 | Mitsubishi Electric Corp | Semiconductor integrated circuit mfg. |
-
1986
- 1986-06-30 JP JP15169086A patent/JPS639126A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19521389A1 (en) * | 1994-12-06 | 1996-06-13 | Mitsubishi Electric Corp | Semiconductor integrated circuit mfg. |
| DE19521389C2 (en) * | 1994-12-06 | 2001-06-07 | Mitsubishi Electric Corp | Method and device for producing a semiconductor integrated circuit |
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