JPH09320983A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an increase in contact resistance without increasing wiring cost. SOLUTION: An n-type diffusion layer 2 is formed near to a surface of a p-type Si semiconductor substrate 1. A natural oxide film 6 on a contact face 5 of a contact hole 4, which is formed by etching an interlayer insulating film 3, is removed in an acid cleaning step and cleaned again in a hydrochloric acid and hydrogen peroxide solution to form an Si oxide film 7. An Al-Si layer is deposited in a sputtering method, and an Al-Si wiring is formed by etching. A heat treatment step is carried out to improve contact characteristics. Since silicon is not exposed at the contact face 5 as an interface between the Si substrate 1 and the Al-Si film 8, a deposition area of solid phase epitaxial silicon is made smaller even when heat treatment is carried out, as compared with a case that the Al-Si film is deposited without forming the Si oxide film 7 and the heat treatment is carried out. As a result, the increase in contact resistance can be prevented.

Description

Detailed Description of the Invention [Industrial applications]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device in which a Si semiconductor substrate and an Al--Si wiring are connected by a contact hole in a wiring process.

[0002]

2. Description of the Related Art In a conventional semiconductor device, a wiring metal is connected to a Si semiconductor substrate at a contact hole portion, and Al is often used as a wiring material. FIG. 3A is a sectional view of a contact hole portion in an example of such a conventional semiconductor device. An N-type diffusion layer 12 is formed near the surface of the p-type Si semiconductor substrate 11, and an interlayer insulating film 13 and a contact hole 14 are formed on the p-type Si semiconductor substrate 11. The Al wiring 16 is connected to the N-type diffusion layer 12 at the contact surface 15.

In order to improve the ohmic characteristics of the contact between the Al wiring 16 and the N-type diffusion layer 12, 400-450
The heat treatment at ℃ is performed after the Al wiring 16 is formed. During this heat treatment, Si of the Si semiconductor substrate diffuses into Al, and after the Si escapes, Al diffuses, so that (b) in FIG.
The alloy spike 17 as shown in FIG. The alloy spike causes a junction short circuit and an increase in leakage current, which deteriorates the performance of the semiconductor device.

As a measure against such a problem, Al is added in a few%.
There is known a method of using the Al-Si alloy containing Si as a wiring material. The amount of Si that begins to dissolve in Al is A
Since it is determined by the solid solubility of Si in Al at the heat treatment temperature after the 1-wiring, the addition of Si in Al in advance can prevent the alloy spike from occurring.

FIG. 4 shows an example of a conventional method of manufacturing a contact hole portion using an Al--Si alloy as a wiring material. FIG. 4A is a partial cross-sectional view of the p-type Si semiconductor substrate. A thermal oxide film 3b having a thickness of 25 nm is formed on the surface of the p-type Si semiconductor substrate 1. After that, by using the ion implantation method, As ⁺ ions are implanted at a predetermined location with an acceleration energy of 70 KeV and a dose amount of 4E15 cm ^-2 .

Next, as shown in (b), an 800 nm-thick PSG film 3a (phosphorus-doped SiO 2) is formed on the thermal oxide film 3b.
₂ film, P ₂ O ₅ : 4 mol%) is deposited. PSG film 3
a is an atmospheric pressure CVD (Chem) which forms a film by a chemical reaction by supplying a source gas to a heated substrate surface in the atmosphere.
It is formed by the ICP vapor deposition method. Then, in an N ₂ atmosphere for 20 minutes, 95
A heat treatment is performed at 0 ° C., and the N type diffusion layer 2 is formed at the place where As ⁺ ions are implanted.

Thermal oxide film 3b and P formed on the oxide film
The interlayer insulating film 3 is composed of two layers of the SG film 3a. The contact hole 21 is opened in the interlayer insulating film 3 by etching. Contact surface 2 at the bottom of contact hole 21
A natural oxide film 23 of Si is formed on the upper side of 2. After washing with a buffered hydrofluoric acid solution (HF: NH ₄ F) and drying, the natural oxide film 23 is removed as shown in FIG. 4C.

Next, as shown in FIG. 4D, an Al-Si film 24 for wiring is deposited by a sputtering method and processed into a wiring pattern by photolithography / etching method, and then (e). Al-Si wiring 25 shown in
Is formed. Then, in order to improve the ohmic characteristics of the contact between the Al-Si wiring 25 and the N diffusion layer 2,
Heat treatment at 400 to 450 ° C. is performed.

[0009]

However, when the Al--Si alloy is used as the wiring metal as described above, alloy spikes can be prevented, but a new problem occurs.
Natural oxide film 2 formed on the bottom surface of contact hole 21
When 3 is removed by acid cleaning, Si of the N-type diffusion layer 2 is exposed on the bottom surface of the contact hole 21, and Al is formed on this.
-Si wiring 25 is formed. Therefore, during the subsequent heat treatment, the Si in the Al-Si alloy is based on the Si exposed at the interface between the Al-Si wiring 25 and the N-type diffusion layer 2.
Solid phase epitaxial growth occurs, and solid phase epi-Si deposition 26 occurs.

FIG. 5 shows an observation view of solid phase epi-Si deposition in a contact hole having a diameter of 3 μm. This schematically shows a state in which the Al—Si wiring is removed from the semiconductor device after the wiring process and the contact surface 22 is observed with an electron microscope. A large area of monolithic solid-phase epi-Si deposition 26 is generated on the contact surface 22 and occupies almost 40% of the area of the contact surface 22. Solid phase epi Si
Since the impurity concentration during deposition is much lower than the impurity concentration in the N-type diffusion layer, solid phase epi-Si deposition causes an increase in contact resistance.
If the ratio of i precipitation is large, the influence of the increase in contact resistance becomes significant, and the performance of the semiconductor device deteriorates.

In recent years, in order to prevent this solid-phase epi-Si precipitation, a barrier metal 27 made of Ti or MoSix as shown in FIG. 6 is formed on the Al-Si wiring 25 and the N-type diffusion layer 2.
The method of being sandwiched between is now used. However, in such a conventional semiconductor manufacturing method using a barrier metal, Ti and MoSix which are barrier metal materials are expensive, and the number of wiring steps is increased, resulting in a considerably high wiring cost. The proportion of the wiring process in the manufacturing process is increasing with the increase in density of semiconductor devices, and cost reduction in the wiring process is desired.

Therefore, in view of the above-mentioned conventional problems, the present invention provides a semiconductor device which suppresses an increase in contact resistance due to solid phase epi-Si deposition in a contact hole without increasing a wiring cost and has a favorable price-performance ratio. It is intended to provide a manufacturing method.

[0013]

To achieve the above object, the present invention provides a step of depositing an interlayer insulating film on a Si semiconductor substrate and forming a contact hole, and a step of forming a contact hole on the bottom surface of the contact hole. And a step of forming a Si oxide film on the bottom surface of the contact hole, and a step of forming an Al-Si wiring on the contact hole and the interlayer insulating film.

Particularly, the step of forming the Si oxide film is
It is desirable to clean the bottom surface of the contact hole with a hydrochloric acid / hydrogen peroxide solution.
It is preferable that the i oxide film has a thickness substantially equal to the thickness of the natural oxide film.

[0015]

[Function] After removing the natural oxide film by acid cleaning, Al-
By forming a thin Si oxide film on the bottom surface of the contact hole before depositing the Si film, Si is not exposed at the boundary surface. Therefore, the solid phase epi-Si deposition during the heat treatment performed after the Al-Si wiring formation can be suppressed, and the solid phase epi-deposition occupying in the contact hole can be limited to a small area. In particular, by cleaning the substrate with a hydrochloric acid / hydrogen peroxide solution, a Si oxide film can be grown on the contact surface without requiring a costly step.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to examples. FIG. 1 is a sectional view showing a manufacturing process of a contact hole portion of an embodiment in which the present invention is applied to a semiconductor device having an N type diffusion layer provided on a p type Si semiconductor substrate.
FIG. 1A is a sectional view of a contact hole portion in which a contact hole is formed by removing the interlayer insulating film above the diffusion layer by an etching technique. FIG. 4 (a) described above.
And a process similar to the conventional example shown in (b), p-type S
An i-semiconductor substrate 1, an N-type diffusion layer 2, an interlayer insulating film 3 composed of two layers of a PSG film 3a and a thermal oxide film 3b, and a contact hole 4 are formed.

The contact hole 4 is subjected to resist patterning for forming a contact hole by photolithography, and then C ₂ F ₆ and CHF ₃ gases are used to perform RIE (Reactive Ion Etch).
ing) method and is formed by etching. On the contact surface 5, which is the bottom surface of the contact hole 4, a 1 nm-thick natural oxide film 6 that grows on the Si surface is formed. That is, FIG. 1A shows the same process steps as FIG. 4B.

In addition to the composition of the natural oxide film 6 being unstable, the reactive products generated during the etching process by the RIE method may remain on the contact surface and be contained in the natural oxide film. Therefore, the Si semiconductor substrate is then acid washed to remove the natural oxide film 6. A buffered hydrofluoric acid solution is used as the cleaning liquid. First, the Si semiconductor substrate is cleaned for 20 seconds and rinsed with pure water for another 10 minutes. FIG. 1B shows a cross section of the contact hole portion after rinsing, and the contact surface 5 is exposed.

Next, a hydrochloric acid / hydrogen peroxide solution (HCl: H
₂ O ₂ : H ₂ O = 1: 1: 5) is used to wash the substrate, a Si oxide film having a thickness of 1 nm is grown on the contact surface, and the substrate is dried using an IPA Baha dryer.
FIG. 1C shows a cross section of the contact hole portion after drying, and the Si oxide film 7 is formed on the contact surface 5.

An Al-Si film (1 wt% Si) having a thickness of 1000 nm is deposited on the surface of the substrate after drying using a magnetron sputtering method, and Al is deposited as shown in (d).
-Si film 8 is formed. Furthermore, resist patterning for forming a wiring pattern on Al-Si film, with H ₃ PO ₄ solution, to etch the Al, and thereafter removing the resist with O ₂ plasma, Al-Si wiring 9 To form. Then, the Si residue left on the interlayer insulating film is removed by CF ₄ gas plasma. In addition, Al-S
An evaporation method can be used for depositing the i film 8 depending on manufacturing conditions.

Then, in order to improve the ohmic characteristics of the contact between the N-type diffusion layer 2 and the Al-Si wiring 9, a heat treatment is performed in a H ₂ atmosphere at 400 ° C. FIG. 1E is a cross-sectional view of the contact hole portion after the heat treatment, in which a small solid phase epi-Si deposition 10 is generated.

FIG. 2 shows an observation view of solid-phase epi-Si deposition in a contact hole having a diameter of 3 μm produced by the manufacturing method of this embodiment. This schematically shows a state in which the Al—Si wiring is removed from the semiconductor device after the wiring process and the contact surface is observed with an electron microscope. It can be seen that although a small amount of solid phase epitaxial deposition 10 is generated on the contact surface 5, the area is about 5% of the area of the contact surface, and is effectively an area that does not cause an increase in contact resistance.

Since this embodiment is configured as described above, by cleaning with a hydrochloric acid / hydrogen peroxide solution before depositing the Al-Si film, it is possible to suppress solid phase epi-Si deposition, It is possible to suppress an increase in contact resistance in a contact hole and manufacture a semiconductor device having an improved price performance ratio without increasing wiring cost.

[0024]

As described above, according to the present invention, the natural oxide film formed on the bottom surface of the contact hole formed in the interlayer insulating film provided on the Si semiconductor substrate is removed by acid cleaning, and then the contact hole is again removed. -Since a thin Si oxide film is formed on the bottom surface of the insulating film by cleaning with hydrochloric acid / hydrogen peroxide solution, and thereafter an Al-Si film is deposited on the contact hole and the interlayer insulating film, the Since Si is not exposed on the bottom surface of the contact hole which is the boundary surface of the Si semiconductor substrate, solid phase epi-Si deposition on the bottom surface of the contact hole can be suppressed to a small area. Therefore, without increasing wiring cost, it is possible to suppress an increase in contact resistance due to solid-phase epi-Si deposition in a contact hole and manufacture a semiconductor device having an improved price / performance ratio.

[Brief description of drawings]

FIG. 1 is a diagram showing a manufacturing process according to an embodiment of the present invention.

FIG. 2 is a schematic diagram showing a state of a contact surface in an example.

FIG. 3 is a cross-sectional view illustrating a conventional semiconductor device.

FIG. 4 is a diagram showing a conventional manufacturing process.

FIG. 5 is a schematic view showing a state of a contact surface by a conventional manufacturing process.

FIG. 6 is a cross-sectional view showing another conventional semiconductor device.

[Explanation of symbols]

 1 p-type Si semiconductor substrate 2 N-type diffusion layer 3 interlayer insulating film 3a PSG film 3b thermal oxide film 4 contact hole 5 contact surface 6 natural oxide film 7 Si oxide film 8 Al-Si film 9 Al-Si wiring 10 solid phase epitaxy Si precipitation 11 p-type Si semiconductor substrate 12 N-type diffusion layer 13 Interlayer insulating film 14, 21 Contact hole 15, 22 Contact surface 16 Al wiring 17 Alloy spike 23 Natural oxide film 24 Al-Si film 25 Al-Si wiring 26 Solid phase Epi Si deposition 27 Barrier metal

Claims (3)

[Claims] 1. A step of depositing an interlayer insulating film on a Si semiconductor substrate to open a contact hole, a step of removing a natural oxide film formed on a bottom surface of the contact hole by acid cleaning, and the contact hole. And a step of forming an Si oxide film on the bottom surface of the semiconductor device and a step of forming an Al-Si wiring on the contact hole and the interlayer insulating film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the Si oxide film comprises cleaning the bottom surface of the contact hole with hydrochloric acid / hydrogen peroxide solution. 3. The Si oxide film is formed to a thickness substantially equal to the thickness of the natural oxide film.
Or a method for manufacturing a semiconductor device according to item 2.