KR970004427B1 - A method for forming metal layer for semiconductor devices - Google Patents

A method for forming metal layer for semiconductor devices Download PDF

Info

Publication number
KR970004427B1
KR970004427B1 KR1019930019535A KR930019535A KR970004427B1 KR 970004427 B1 KR970004427 B1 KR 970004427B1 KR 1019930019535 A KR1019930019535 A KR 1019930019535A KR 930019535 A KR930019535 A KR 930019535A KR 970004427 B1 KR970004427 B1 KR 970004427B1
Authority
KR
South Korea
Prior art keywords
pure water
metal
ozone
metal wiring
forming
Prior art date
Application number
KR1019930019535A
Other languages
Korean (ko)
Other versions
KR950009955A (en
Inventor
박상훈
문창순
Original Assignee
현대전자산업 주식회사
김주용
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 현대전자산업 주식회사, 김주용 filed Critical 현대전자산업 주식회사
Priority to KR1019930019535A priority Critical patent/KR970004427B1/en
Publication of KR950009955A publication Critical patent/KR950009955A/en
Application granted granted Critical
Publication of KR970004427B1 publication Critical patent/KR970004427B1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02057Cleaning during device manufacture
    • H01L21/02068Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A forming method of metal wires is provided to improve reliability of devices by preventing corrosion of aluminum wire. The method comprises the steps of: forming a metal film on a semiconductor substrate having lower layer; cleaning the surface of the metal film using a DIW(de-ionized water) contained ozone(O3); patterning the cleaned metal film using a metal wiring mask; and cleaning the resultant structure using a DIW contained fluorine(F). Thereby, it is possible to improve reliability of devices by preventing corrosion of metal wire.

Description

반도체 장치의 금속배선 형성방법Metal wiring formation method of semiconductor device

제1도는 종래 기술에 따른 금속배선 부식 장지를 위한 공정 흐름도.1 is a process flow diagram for metal wiring corrosion prevention according to the prior art.

제2도는 본 발명의 일실시예에 따른 금속배선 부식 방지를 위한 공정 흐름도.2 is a process flow diagram for metal wiring corrosion protection according to an embodiment of the present invention.

본 발명은 반도체 장치의 제조공정중 소자간의 전기적 연결을 위한 금속배선 형성방법에 관한 것으로, 특히 불소와 오존을 순수에 용해시켜 금속막 표면에 자연산화막을 형성하여 금속배선의 부식을 방지하는 반도체 장치의 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring for electrical connection between devices during a manufacturing process of a semiconductor device. In particular, a semiconductor device for preventing corrosion of metal wiring by forming a natural oxide film on the surface of a metal film by dissolving fluorine and ozone in pure water. It relates to a metal wiring forming method of.

반도체 소자용 금속배선 물질로 널리 사용되는 알루미늄(Al)은 염소(Cl2)에 의해 부식되어 소자가 불량해지는 원인으로 작용하므로 이를 방지하기 위한 여러 방안이 모색되고 있다.Aluminum (Al), which is widely used as a metallization material for semiconductor devices, acts as a cause of deterioration of devices due to corrosion by chlorine (Cl 2 ), and various methods for preventing this are being sought.

상기 금속배선의 부식문제 방지 노력에 부응한 종래의 한 방법은 다음과 같다.One conventional method in response to efforts to prevent the corrosion problem of the metal wiring is as follows.

첨부된 도면 제1도의 공정 흐름도에 도시된 바와 같이 먼저, 금속배선 형성을 위한 금속막인 알루미늄막을 증착하고, 그 상부에 저온 산화막을 증착한 후, 사진 식각 및 세정 단계를 거쳐 금속배선을 형성하고, 금속배선의 부식을 방지하기 위한 보호막을 증착하는 단계로 구성된다.As shown in the process flow diagram of FIG. 1 of the accompanying drawings, first, an aluminum film, which is a metal film for forming metal wiring, is deposited, and a low temperature oxide film is deposited thereon, followed by photolithography and cleaning to form metal wiring. And depositing a protective film to prevent corrosion of the metallization.

그러나, 상기한 종래의 방법은 알루미늄막을 패터닝하기 위한 사진 식각 공정 전후 단계에서 저온 산화막 및 보호막을 증착함으로써, 공정 시간이 길어질 뿐 아니라 화학 기상 증착(Chemical Vapor Deposition) 공정시 이물질 발생 위험이 커지게 된다.However, the above-described conventional method deposits a low temperature oxide film and a protective film in a step before and after a photolithography process for patterning an aluminum film, thereby increasing the process time and increasing the risk of foreign matter generation during a chemical vapor deposition process. .

또한, 식각 공정시 불소(F)기에 의한 염소(Cl)기의 치환 작용시 불량할 경우 금속배선의 치명적인 결함인 부식을 초래하게 된다.In addition, when the chlorine (Cl) group by the fluorine (F) group during the etching process is poor when the etching process causes a corrosion, which is a fatal defect of the metal wiring.

상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 염소기에 의한 알루미늄막의 부식을 방지하는 반도체 장치의 금속배선 형성방법을 제공하는데 그 목적이 있다.The present invention devised to solve the above problems is to provide a method for forming a metal wiring of a semiconductor device to prevent corrosion of the aluminum film by chlorine groups.

상기 목적을 달성하기 위하여 본 발명은 반도체 장치의 금속배선 형성방법에 있어서, 반도체 기판 상에 형성된 소정의 하부층 상에 금속막을 형성하는 단계; 오존을 포함하는 순수를 사용하여 상기 금속막 표면을 세정하는 단계; 금속배선 마스크를 사용하여 상기 금속막을 패터닝하는 단계를 포함하여 이루어진다.In order to achieve the above object, the present invention provides a method for forming a metal wiring in a semiconductor device, comprising: forming a metal film on a predetermined lower layer formed on a semiconductor substrate; Cleaning the surface of the metal film using pure water containing ozone; Patterning the metal film using a metallization mask.

이하, 본 발명의 일실시예를 상술한다.Hereinafter, an embodiment of the present invention will be described in detail.

우선, 본 발명의 기술적 원리는 다음의 식 1,2,3,으로 대별된다.First, the technical principle of the present invention is roughly divided into the following equations 1,2,3.

불소(F)는 상온의 순수(DI water)에서 다음과 같이 분해된다.Fluorine (F) is decomposed in pure water at room temperature as follows.

2F2+2H2O⇔4H++O2…………………………………………………………식 12F 2 + 2H 2 O⇔4H + + O 2 . … … … … … … … … … … … … … … … … … … … … … Equation 1

상기 반응 특성을 이용하여 알루미늄막 표면에 자연 산화막을 성장시킬 수 있다.By using the reaction characteristics, a natural oxide film may be grown on the surface of the aluminum film.

4Al+3O2⇒2Al2O3……………………………………………………………식 2 4Al + 3O 2 ⇒2Al 2 O 3 ... … … … … … … … … … … … … … … … … … … … … … … Equation 2

이때, 강산화제인 오존(O3)을 첨가하면 자연 산화막 형성이 촉진되어 짧은 시간에 알루미늄막 표면에 자연 산화막이 성장될 수 있다.At this time, the addition of ozone (O 3 ), a strong oxidizing agent, promotes the formation of the natural oxide film, and thus, the natural oxide film may be grown on the surface of the aluminum film in a short time.

O3+2H++2e⇒O2+H2O………………………………………………………식 3O 3 + 2H + + 2e⇒O 2 + H 2 O... … … … … … … … … … … … … … … … … … … … … Expression 3

상기 식 1,2,3에 나타난 기술적 원리를 이용하여 본 발명을 구현하는 일실시예의 공정 절차는 도면 제2도에 도시된 바와 같다.A process procedure of an embodiment for implementing the present invention using the technical principles shown in Equations 1, 2 and 3 is shown in FIG.

먼저 금속배선을 형성하고자 하는 부위에 알루미늄막을 증착하고, 오존(O3)을 함유한 순수에 세정 후, 사진 및 식각 공정을 진행하여 알루미늄막 패턴을 형성하고, 불소(F)를 함유한 순수에 세정을 실시한 다음, 금속배선 마스크로 사용된 포토레지스트 패턴을 제거하는 공정으로 진행된다.First, an aluminum film is deposited on the site where the metal wiring is to be formed, washed with pure water containing ozone (O 3 ), and then subjected to photographic and etching processes to form an aluminum film pattern, and to pure water containing fluorine (F). After cleaning, the process proceeds to removing the photoresist pattern used as the metallization mask.

즉, 알루미늄 증착후 오존을 함유한 순수로 60℃ 이하의 온도에서 세정하여 알루미늄 금속배선 상부에 자연 산화막을 성장시킨 다음, 사진 및 식각 공정을 실시하여 알루미늄막 패턴을 형성하고, 불소를 함유한 20℃ 이하 온도의 순수에 세정함으로써 이전 단계인 식각 공정시 잔류하는 염소기를 불소기로 치환함과 동시에 알루미늄막의 표면에 추가로 자연 산화막을 성장시킴으로써 양질의 알루미늄 금속배선을 형성할 수 있다.That is, after deposition of aluminum, pure water containing ozone is washed at a temperature of 60 ° C. or lower to grow a natural oxide film on the upper part of the aluminum metal wiring, and then a photographic and etching process is performed to form an aluminum film pattern. It is possible to form a high quality aluminum metal wiring by replacing the chlorine group remaining in the etching process as a fluorine group in the previous step by rinsing with pure water at a temperature of not more than ℃ and growing a natural oxide film on the surface of the aluminum film.

이때, 오존의 용해도는 아래 표 1에 도시된 바와 같이 60℃에서 0이 되고 수온에 반비례하므로 수온을 60℃이하가 되게 해야 한다.At this time, the solubility of ozone becomes 0 at 60 ° C and inversely proportional to the water temperature, as shown in Table 1 below, so that the water temperature should be 60 ° C or less.

[표 1] 순수한 물에서의 오존의 용해도Table 1 Solubility of Ozone in Pure Water

또한 불소는 상온에서도 순수에 잘 용해되므로 20℃ 이상의 온도로 한다.In addition, fluorine is dissolved in pure water even at room temperature, so the temperature is 20 ° C or higher.

한편, 상기 공정에서 순수에 불소와 오존을 동시에 용해시켜 더욱 활성화시킴으로써 양질의 자연 산화막을 얻을 수 있으며, 공정의 간소화를 기할 수 있다.On the other hand, by dissolving fluorine and ozone in pure water at the same time and further activating to obtain a natural oxide film of high quality, it is possible to simplify the process.

또한, 불소 및 오존이 용해된 순수를 사용한 세정은 알루미늄 배선 형성시의 어느 한 단계에 임의로 삽입되어도 본 발명이 이루고자 하는 목적에는 하등의 영향을 미치지 않는다.In addition, cleaning using pure water in which fluorine and ozone are dissolved does not affect the object to be achieved by the present invention even if it is arbitrarily inserted at any one step in forming aluminum wiring.

상기와 같이 이루어지는 본 발명의 금속배선 형성방법은 염소기에 의한 알루미늄배선의 부식현상을 방지하여 소자의 신뢰성을 향상시키는 효과를 얻을 수 있다.Metal wiring forming method of the present invention made as described above can prevent the corrosion of the aluminum wiring by the chlorine group to obtain the effect of improving the reliability of the device.

Claims (7)

반도체 장치의 금속배선 형성방법에 있어서, 반도체 기판상에 형성된 소정의 하부층 상에 금속막을 형성하는 단계; 오존을 포함하는 순수를 사용하여 상기 금속판 표면을 세정하는 단계; 금속배선 마스크를 사용하여 상기 금속막을 패터닝하는 단계를 포함하여 이루어진 반도체 장치의 금속배선 형성방법.CLAIMS 1. A method for forming metal wiring in a semiconductor device, comprising: forming a metal film on a predetermined lower layer formed on a semiconductor substrate; Cleaning the surface of the metal plate using pure water containing ozone; And patterning the metal film using a metal wiring mask. 제1항에 있어서, 상기 금속막을 패터닝하는 단계 이후에 불소를 포함하는 순수를 사용하여 세정하는 단계를 더 포함하여 이루어진 것을 특징으로 하는 반도체 장치의 금속배선 형성방법.The method of claim 1, further comprising, after the patterning of the metal film, cleaning using pure water containing fluorine. 제1항 또는 제2항에 있어서, 상기 오존을 포함하는 순수는 불소를 더 포함하는 것을 특징으로 하는 반도체 장치의 금속배선 형성방법.The method of claim 1 or 2, wherein the ozone-containing pure water further comprises fluorine. 제2항에 있어서, 상기 불소를 포함하는 순수는 오존을 더 포함하는 것을 특징으로 하는 반도체 장치의 금속배선 형성방법.The method of claim 2, wherein the pure water containing fluorine further comprises ozone. 제3항에 있어서, 상기 불소를 포함하는 순수는 오존을 더 포함하는 것을 특징으로 하는 반도체 장치의 금속배선 형성방법.4. The method of claim 3, wherein the pure water containing fluorine further comprises ozone. 제1항 또는 제2항 또는 제4항에 있어서, 상기 오존을 포함하는 순수의 온도는 60℃를 넘지 않는 것을 특징으로 하는 반도체 장치의 금속배선 형성방법.The method of claim 1, 2, or 4, wherein the temperature of the pure water containing ozone does not exceed 60 ° C. 6. 제2항 또는 제4항에 있어서, 상기 불소를 포함하는 순수의 온도는 적어도 20℃인 것을 것을 특징으로 하는 반도체 장치의 금속배선 형성방법.The method of claim 2 or 4, wherein the temperature of the pure water containing fluorine is at least 20 ° C.
KR1019930019535A 1993-09-23 1993-09-23 A method for forming metal layer for semiconductor devices KR970004427B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930019535A KR970004427B1 (en) 1993-09-23 1993-09-23 A method for forming metal layer for semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930019535A KR970004427B1 (en) 1993-09-23 1993-09-23 A method for forming metal layer for semiconductor devices

Publications (2)

Publication Number Publication Date
KR950009955A KR950009955A (en) 1995-04-26
KR970004427B1 true KR970004427B1 (en) 1997-03-27

Family

ID=19364457

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930019535A KR970004427B1 (en) 1993-09-23 1993-09-23 A method for forming metal layer for semiconductor devices

Country Status (1)

Country Link
KR (1) KR970004427B1 (en)

Also Published As

Publication number Publication date
KR950009955A (en) 1995-04-26

Similar Documents

Publication Publication Date Title
JP3181264B2 (en) Etching aqueous solution and etching method for removing inorganic polymer residue
US5176756A (en) Method for fabricating a semiconductor device including a step for cleaning a semiconductor substrate
US5650356A (en) Method for reducing corrosion in openings on a semiconductor wafer
KR19990075991A (en) Metal wiring formation method of semiconductor device
US5567244A (en) Process for cleaning semiconductor devices
JPH0770511B2 (en) Plasma etching process for single crystal silicon with improved selectivity to silicon dioxide
US5863834A (en) Semiconductor device and method of manufacturing the same
US6218085B1 (en) Process for photoresist rework to avoid sodium incorporation
KR970004427B1 (en) A method for forming metal layer for semiconductor devices
KR100262506B1 (en) Manufacturing method for semiconductor device
US6713397B2 (en) Manufacturing method of semiconductor device
US20030027429A1 (en) Process for removing polymers during the fabrication of semiconductor devices
KR100203905B1 (en) Method for forming multi-layer metal interconnection
JPH0513534B2 (en)
KR20010004746A (en) Method of forming a via-hole in a semiconductor device
JP2841529B2 (en) Selective metal film formation method
JPH10261627A (en) Manufacturing method of semiconductor device
KR20010089238A (en) Process comprising an improved pre-gate clean
KR100190102B1 (en) Cleaning solution and cleaning method using the same
JP3206008B2 (en) Method of forming multilayer wiring
KR950014943B1 (en) Method of removing silicon residue formed by etching metal layer
JP4128698B2 (en) Manufacturing method of semiconductor device
KR100281515B1 (en) Tungsten film pattern formation method of semiconductor device
KR100231846B1 (en) Interconnecting method of semiconductor device
DE10255865A1 (en) A process for structuring dielectric layers on a semiconductor substrate and for etching of small diameter contact holes and drains with high precision

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20090223

Year of fee payment: 13

LAPS Lapse due to unpaid annual fee